Hardware implementation of a SHA-3 application-specific instruction set processor

Elmohr, Mahmoud A.; Saleh, Mostafa A.; Eissa, Ahmed S.; Ahmed, Khaled E.; Farag, Mohammed M.

doi:10.1109/icm.2016.7847921

Cited by 7 publications

(9 citation statements)

References 3 publications

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“…All results and comparisons are shown in Table II and Table III. All references [12]- [14] use the ! !…”

Section: Implementations and Resultsmentioning

confidence: 99%

“…In 2015, Wang et al [13] were the first to propose custom extensions for SHA-3 implemented in FPGA. In 2016, Elmohr et al [14] proposed two ASIPs based on a 32-bit processor for SHA-3. The first one (Native ISE) uses four custom instructions, and the second one (Co-processor ISE) adds auxiliary registers to supply parallel implementations.…”

Section: B Related Workmentioning

confidence: 99%

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Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions

Mentens

Picek

2023

2023 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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SHA-3 is considered to be one of the most secure standardized hash functions. It relies on the Keccak-f[1 600] permutation, which operates on an internal state of 1 600 bits, mostly represented as a 5 × 5 × 64−bit matrix. While existing implementations process the state sequentially in chunks of typically 32 or 64 bits, the Keccak-f[1 600] permutation can benefit a lot from speedup through parallelization. This paper is the first to explore the full potential of parallelization of Keccak-f[1 600] in RISC-V based processors through custom vector extensions on 32-bit and 64-bit architectures. We analyze the Keccakf[1 600] permutation, composed of five different step mappings, and propose ten custom vector instructions to speed up the computation. We realize these extensions in a SIMD processor described in SystemVerilog. We compare the performance of our designs to existing architectures based on vectorized applicationspecific instruction set processors (ASIP). We show that our designs outperform all related work in throughput due to our carefully selected custom vector instructions.

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“…All results and comparisons are shown in Table II and Table III. All references [12]- [14] use the ! !…”

Section: Implementations and Resultsmentioning

confidence: 99%

Section: B Related Workmentioning

confidence: 99%

Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions

Mentens

Picek

2023

2023 Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE)

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“…As a result, computer architects can freely design specific instructions to accelerate domain-specific applications in multiple areas such as bioinformatics, machine learning, or graph analysis. In particular, commercial frameworks, such as Codasip, offer simple software-hardware co-design opportunities using a high level specification language, which generates Register Transfer Language (RTL) code, providing compiler support [11].…”

Section: Introductionmentioning

confidence: 99%

Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI

Soria-Pardos

Doblas

López-Paradís

et al. 2022

2022 25th Euromicro Conference on Digital System Design (DSD)

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The RISC-V open Instruction Set Architecture (ISA) has proven to be a solid alternative to licensed ISAs. In the past 5 years, a plethora of industrial and academic cores and accelerators have been developed implementing this open ISA.In this paper, we present Sargantana, a 64-bit processor based on RISC-V that implements the RV64G ISA, a subset of the vector instructions extension (RVV 0.7.1), and custom applicationspecific instructions. Sargantana features a highly optimized 7-stage pipeline implementing out-of-order write-back, register renaming, and a non-blocking memory pipeline. Moreover, Sargantana features a Single Instruction Multiple Data (SIMD) unit that accelerates domain-specific applications. Sargantana achieves a 1.26 GHz frequency in the typical corner, and up to 1.69 GHz in the fast corner using 22nm FD-SOI commercial technology.As a result, Sargantana delivers a 1.77× higher Instructions Per Cycle (IPC) than our previous 5-stage in-order DVINO core, reaching 2.44 CoreMark/MHz. Our core design delivers comparable or even higher performance than other state-ofthe-art academic cores performance under Autobench EEMBC benchmark suite. This way, Sargantana lays the foundations for future RISC-V based core designs able to meet industrialclass performance requirements for scientific, real-time, and highperformance computing applications.

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“…[16] extends a 32bit LEON3 processor achieves about 87% performance improvement and 9.5% code size reduction with instruction extensions for 64-bit rotation. [17] implements 2 ASIPs. One shares the main processor datapath and the other customize a co-processor datapath.…”

Section: Introductionmentioning

confidence: 99%

“…† Research[16] and[17] only evaluate performance on FPGA prototypes without any evaluation of power.…”

mentioning

confidence: 99%

Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor

Rao

Xu³

et al. 2018

IEICE Trans. Inf. & Syst.

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Data integrity is a key metric of security for Internet of Things (IoT) which refers to accuracy and reliability of data during transmission, storage and retrieval. Cryptographic hash functions are common means used for data integrity verification. Newly announced SHA-3 is the next generation hash function standard to replace existing SHA-1 and SHA-2 standards for better security. However, its underlying Keccak algorithm is computation intensive and thus limits its deployment on IoT systems which are normally equipped with 32-bit resource constrained embedded processors. This paper proposes two efficient SHA-3 ASIPs based on an open 32-bit RISC-V embedded processor named Z-scale. The first operation-oriented ASIP (OASIP) focuses on accelerating time-consuming operations with instruction set extensions to improve resource efficiency. And next datapath-oriented ASIP (DASIP) targets exploiting advance data and instruction level parallelism with extended auxiliary registers and customized datapath to achieve high performance. Implementation results show that both proposed ASIPs can effectively accelerate SHA-3 algorithm with 14.6% and 26.9% code size reductions, 30% and 87% resource efficiency improvements, 71% and 262% better maximum throughputs as well as 40% and 288% better power efficiencies than reference design. This work makes SHA-3 algorithm integration practical for both low-cost and high-performance IoT systems.

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Hardware implementation of a SHA-3 application-specific instruction set processor

Cited by 7 publications

References 3 publications

Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions

Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash Functions

Sargantana: A 1 GHz+ In-Order RISC-V Processor with SIMD Vector Extensions in 22nm FD-SOI

Design Exploration of SHA-3 ASIP for IoT on a 32-bit RISC-V Processor

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