Hardware Evolution Based on Improved Simulated Annealing Algorithm in Cyclone V FPSoCs

Abstract

Evolvable hardware (EHW) is an emerging area of research that uses evolutionary algorithms (EAs) to construct circuits without manual intervention. However, this technique confronts two major issues: the evolution efficiency of structures and the computational efficiency of EAs. To address these issues, we construct a novel virtual reconfigurable circuit (VRC) based on artificial neural network (ANN) architecture and develop a promising EA based on improved simulated annealing (ISA) for the research of EHW. Here, ISA escapes the local optimization through an inner loop and expands new search space through an outer loop. Furthermore, several strategies are proposed for the representation, perturbation and selection of solutions (individuals) to reduce the computational burden throughout the entire evolution process. The use of an Intel Cyclone V field programmable system-on-chip (FPSoC) further accelerates the execution of the algorithm and provides designers with much more high-level processing power than that provided by soft-cores. The obtained results show that the proposed method achieves high-speed processing and improves computational efficiency. The results also show that the method has good flexibility and scalability. INDEX TERMS Evolvable hardware, artificial neural networks, improved simulated annealing, algorithm design and analysis, FPSoC.

Hypernetworks Learn the Binary Two-Spiral Classification Task

“…This compatibility between FPGAs and hypernetwork algorithms makes them a potentially feasible implementation of the hypernetwork architecture, possibly realizing the physical realization of evolvable hardware. FPGAs have been widely used in the field of evolvable computing, which involves the use of evolutionary algorithms to design and optimize hardware systems (Dobai & Sekanina, 2015;Shang et al, 2020;Yao & Higuchi, 1999). The reconfigurable nature of FPGAs makes them well suited for evolvable computing, as they can be dynamically reprogrammed to implement different hardware configurations and adapt to changing requirements.…”

Research on Evolvable Hardware Based on Improved Evolutionary Strategy

“…1 shows two evaluation methods, the difference of them is the location of evaluation. Usually, the intrinsic EHW is used because it does not require special modeling software [6], and it can get a more appropriate solution based on the current state of the reconfigurable hardware. The research of evolvable hardware mainly focuses on three aspects [7]: propose more efficient evolutionary Since the output of combinational logic circuit is only related to the current input, the expected function can be realized only when the truth table is fully matched, so using the truth table for fitness evaluation is still the mainstream method.…”

“…Most researches to improve evolutionary efficiency scholars are usually based on the first two, among which the improvement of evolutionary algorithm is the majority. The traditional Monkey King genetic algorithm was improved in [6], which divides the population into some sub populations. The co-evolution of multiple populations was adopted to obtain faster convergence speed and better evolutionary performance.…”