Hardware-efficient systolic architectures for inversion in GF(2m)

Yan, Zhiyuan; Sarwate, D.V.; Liu, Z.

doi:10.1049/ip-ifs:20055017

Cited by 15 publications

(10 citation statements)

References 6 publications

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“…A number of architectures have been proposed to perform this EEA based inversion. For example, systolic architecture for inverters with an area-time complexity of O(m 2 ) have been proposed [24,22]. As this algorithm has no modular operations, the implementations have a shorter critical path delay and a smaller area than other EEA based implementations [9,5,12].…”

Section: Algorithm 2 Eea-based Inversion Algorithm [23]mentioning

confidence: 99%

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A digit-serial architecture for inversion and multiplication in GF(2<sup>M</sup>)

Fan

Verbauwhede

2008

2008 IEEE Workshop on Signal Processing Systems

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Modular multiplication and inversion are the essential operations in many Public Key Cryptosystems (PKCs). In this paper, we describe a unified digit-serial inverter/multiplier in GF (2 m). The inversion is based on a modified Extended Euclidean Algorithm (EEA), while the multiplication is based a LSB-first multiplication algorithm. As the inverter and multiplier share the data-path, it is smaller than Arithmetic Logic Units (ALUs) with separated inverters and multipliers. When choosing digit size to be w, this inverter/multiplier finishes one inversion and one multiplication in ⌈ 2m−1 w ⌉ and ⌈ m w ⌉ clock cycles, respectively.

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Section: Algorithm 2 Eea-based Inversion Algorithm [23]mentioning

confidence: 99%

“…Note that the counter is implemented as a so-called ring counter [24]. The value of counter is defined as follow.…”

Section: Bit-serial Invertermentioning

confidence: 99%

A digit-serial architecture for inversion and multiplication in GF(2<sup>M</sup>)

Fan

Verbauwhede

2008

2008 IEEE Workshop on Signal Processing Systems

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“…In recent years, different hardware implementations of the field inversion over F 2 m are presented in literature [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20]. The works [2][3][4][5][6][7][8][9][10][11][12][13][14][15] are implemented in polynomial basis (PB). Several structures for the field inversion based on systolic architecture have been presented.…”

Section: Introductionmentioning

confidence: 99%

“…In this work, a hardware implementation of PB Euclidean‐based inversion based on a modified algorithm is proposed. Two iterations in the previously reported EEA‐based inversion algorithm [8, 13] correspond to one iteration in the modified algorithm. The proposed structure is implemented based on the modified algorithm with low path‐delay.…”

Section: Introductionmentioning

confidence: 99%

Efficient hardware structure for extended Euclidean‐based inversion over

Rashidi

2019

IET Computers & Digital Techniques

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In this study, an efficient hardware structure for implementation of extended Euclidean algorithm (EEA) inversion based on a modified algorithm is presented. In the proposed algorithm, one iteration performs the operations corresponding to two iterations in previously reported EEA-based inversion algorithm. The proposed structure is implemented based on a modified algorithm with low path-delay and hardware consumption. The circuit performs one iteration of the algorithm in one clock cycle. Furthermore, to increase speed and reduce the latency of the structure, the authors applied the loop unrolling technique by replicating the body of the loop. Loop unrolling replaces a loop body by several copies of the body. The authors chose the number of copies based on the trade-off between hardware resources, critical path delay and the number of clock cycles. Therefore, the time and area parameters can be adjusted by different choices. The proposed architecture is simple, low cost and also the number of clock cycles in the structure are reduced compared to existing EEA-based works. The structure over two binary finite fields F 2 163 and F 2 233 has been successfully verified and implemented on Virtex-5 XC5VLX110 fieldprogrammable gate array. The comparison with other previous implementations of the inversion operation verifies that the proposed method has better improvement in terms of area × time complexity.

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“…Therefore, there are many algorithms are presented in the literature to perform field division with their high performance realization in both software and hardware. These algorithms can be computed based on several schemes such as Fermat's little theorem [1,2], Extended Euclid's algorithm (EEA) [3,4,5,6,7], and Extended Stein's algorithm (ESA) [8,9,10,11,12].…”

Section: Introductionmentioning

confidence: 99%

New systolic array architecture for finite field division

Ibrahim

Elsimary

Gebali

2018

IEICE Electron. Express

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This paper proposes a new systolic array architecture to perform division operations over GF(2 m ) based on the modified Stein's algorithm. The systolic structure is extracted by applying a regular approach to the division algorithm. This approach starts by obtaining the dependency graph for the intended algorithm and assigning a time value to each node in the dependency graph using a scheduling function and ends by projecting several nodes of the dependency graph to a processing element to constitute the systolic array. The obtained design structure has the advantage of reducing the number of flip-flops required to store the intermediate variables of the algorithm and hence reduces the total gate counts to a large extent compared to the other related designs. The analytical results show that the proposed design outperforms the related designs in terms of area (at least 32% reduction in area) and speed (at least 60% reduction in the total computation time) and has the lowest AT complexity that ranges from 80% to 94%.

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Hardware-efficient systolic architectures for inversion in GF(2m)

Cited by 15 publications

References 6 publications

A digit-serial architecture for inversion and multiplication in GF(2<sup>M</sup>)

A digit-serial architecture for inversion and multiplication in GF(2<sup>M</sup>)

Efficient hardware structure for extended Euclidean‐based inversion over

New systolic array architecture for finite field division

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