Hardware Designs of Cyclic Redundancy Check Code with Calculation Time Trade-Off Strategy

Abstract

This paper will discuss the design of cyclic redundancy check code (CRC), a most popular error detecting scheme in intelligent communication. At first, the concepts of CRC are given in detail with mathematical model and software simulation in python scripts. And mainly, with calculation time trade-off strategy, we provide the CRC hardware design with three architecture models serial, parallel, hybrid serial and parallel. Keywords: Error Detection Scheme; Cyclic Redundancy Check; Python; Verilog HDL; Digital System Design