Hardware Design of the H.264/AVC Variable Block Size Motion Estimation for Real-Time 1080HD Video Encoding

Abstract

Amongst the video compression standards, the latest one is the H.264/AVC [1]. This standard reaches the highest compression rates when compared to the previous standards. On the other hand, it has a high computational complexity. This high computational complexity makes it difficult the development of software applications running in a current processor when high definitions videos are considered. Thus, hardware implementations become essential. Addressing the hardware architectures, this work presents the architectural design for the variable block size motion estimation (VBSME) defined in the H.264/AVC standard. This architecture is based on full search motion estimation algorithm and SAD calculation. This architecture is able to produce the 41 motion vectors within a macroblock as specified in the standard. The implementation of this architecture was based on standard cell methodology in 0.18μm CMOS technology. The architecture reached a throughput of 34 1080HD frames per second.

An efficient VLSI processor chip for variable block size integer motion estimation in H.264/AVC

“…with which a very low latency is obtained with a high area cost. Architecture with throughput of 72.52 M samples per second that can process 34 1080HD frames per second is presented in [39]. The processor chip proposed in this paper uses a configurable 2D systolic array, modified Lagrangian MV cost and a motion decision module to compute the best mode and best MVs of a MB having a processing capacity for HDTV with a search range of 32 Â 32.…”

“…Indeed, many VLSI implementations propose 2D systolic arrays to be more suitable for high-end real-time usage. References which adopt the complete FSBMA include the 2D architecture with a simple regular control in [16], the novel memory-access with minimum off-chip memory bandwidth in [19], the highperformance reconfigurable architecture to support a scan format for a high data reuse within the search area in [20], the bit serial architecture in [22] and the high throughput design in [39]. Modifications of the FSBMA to reduce either hardware or computing time, at the cost of introducing some video quality loss, can be found in the soft algorithm to simplify the predicted MV and the early termination of motion search used in [21], the multi-resolution IME algorithm presented in [23], the adaptive size in the search area depending on the degree of motion activity in [24,25], the modified algorithm to reduce hardware based on data dependency of motion vector prediction, pixel truncation and subsample proposed in [18], the IP with coarse and fine searches in [26] and the inter-candidate 4-parallel data reuse scheme with 16 2D PE-arrays in [27].…”

Memory-aware multiple reference frame motion estimation for the H.264/AVC standard

“…This way, a fair comparison with [9] is not possible to be performed. The paper [10] presents a MRF-ME approach using SRF core. It proposes a scheme for data reuse in such levels to minimize the bandwidth with the external memory.…”

An efficient hardware architecture for inter-prediction in H.264/AVC encoders

“…However, because many coding tools have been adopted it makes the encoding system much more complex, especially the interprediction part of the system. Many VLSI implementations of the inter-prediction of H.264/AVC encoding systems have been recently proposed to get high-throughput design for real-time high-definition (HD) video applications such as in [3]- [6]. A conventional implementation is normally composed of Motion Estimation (including Integer Motion Estimation (IME) and Fractional Motion Estimation (FME)) and Motion Compensation (MC).…”