Hardware design of the generic rear transition module for the global trigger system of the ATLAS phase II upgrade

Yin, Weigang; Tang, Shaochun; Bonini, F.; Begel, M.; Benoit, M.; Matakias, D.; Zhivun, E.; Xu, H.; Chen, H.

doi:10.1088/1748-0221/17/03/c03017

Cited by 2 publications

(2 citation statements)

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“…The plaintext can be recovered by XOR operation of the mask message and the received encrypted message. It should be noted that the same mask function should be used in the process of encryption and decanting [17].…”

Section: Resultsmentioning

confidence: 99%

Hardware Optimization and System Design of Elliptic Curve Encryption Algorithm Based on FPGA

Gao

2022

Journal of Sensors

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Since entering the era of big data, the degree of information sharing is getting higher and higher; the information exchange is becoming more and more convenient, but at the same time, personal information is also easy to be exposed to the network environment, if it is used by criminals to lead to information leakage, and then bring certain risks. Therefore, it is in the information age and do a good job of network information security and confidentiality. At present, the security and secrecy of network information are mainly realized by cryptography. Public key cryptography can encrypt information and ensure the security of information transmission, so it is widely used in the contemporary society. At present, elliptic curve encryption is highly respected in the research field of public key cryptosystem. Elliptic curve encryption is divided into two main points, multiplication and inversion, respectively. Through the comparison of these two algorithms, it can be found that there are several choices if the main research objective is to save time, and the Euclidean extension method is mainly discussed in this paper. In other words, more efficient algorithms are used in the hardware implementation process, and a variety of algorithms can be used instead of a single curve algorithm. In this process, we can find the special features of upper level operation and bottom level finite operation. The upper level operation is KP operation, while the bottom level operation is fast calculation of four kinds of K in finite field operation, and finally realize FPGA algorithm. With the help of Quartus ii developed by predecessors, the upper and lower operations of elliptic curve are carried out using VHDL language. Combined ANXIX9.62 in the elliptic curve of each module to test, so as to ensure the accuracy of the data, reduces the error. According to the test results, the designed chip can efficiently complete the elliptic curve encryption system in the whole process. And the average KP operation time can reach 15.15 ms at 20 MHz frequency. At the same time, the chip can complete the operation on ECC public key with any variable curve in F domain less than 256. Therefore, this chip is a high-speed elliptic curve cryptographic chip with optional system parameters. Based on this, this article on the elliptic curve encryption algorithm based on FPGA hardware implementation of system design, from the view of mathematical study analysis, was carried out on the elliptic curve cryptosystem, according to the above two big difficulty, namely, the polynomial of GF(2), the finite field multiplication, and inversion; there will be a detailed studies of discussion, through software comparison to find the differences between different software, especially the software implementation performance level. In addition, it will also focus on the design of elliptic curve algorithm PGA, so as to explore the solution of the algorithm hardware.

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Section: Resultsmentioning

confidence: 99%

Hardware Optimization and System Design of Elliptic Curve Encryption Algorithm Based on FPGA

Gao

2022

Journal of Sensors

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“…Typical results of eye scans at a BER of 1 × 10 −9 are summarized in table 1 and figure 3. The testing of the MGT links between the GCM and GRM had been performed and presented at TWEPP in 2021 [10]. lpGBT tests.…”

Section: Grm Hardware Testingmentioning

confidence: 99%

Hardware design and testing of the generic rear transition module for the global trigger subsystem of ATLAS Phase-II Upgrade

Bonini

Tang

2023

J. Inst.

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In the framework of the ATLAS experiment’s Phase-II Upgrade at the High-Luminosity Large Hadron Collider (HL-LHC), new and improved trigger hardware and algorithms will be implemented onto a single-level, 10 μs-latency architecture. The Global Trigger is a new subsystem which will bring event-filter capabilities by performing offline-like algorithms on full-granularity calorimeter data. The implementation of the functionality is firmware-focused and composed of several processing nodes, which are hosted on identical hardware, made up of an Advanced Telecommunications Computing Architecture (ATCA) front board, called Global Common Module (GCM), and a rear transition module (RTM), called Generic RTM (GRM). The GRM, which was developed to mitigate the risks deriving from the complex design and power management of the GCM, features an advanced Xilinx Versal Prime system-on-chip and can handle communication with the GCM and Front-End Link eXchange (FELIX) subsystem and trigger processors through 124 25.8 Gb/s transceiver links, for readout and control. Additionally, the GRM mounts a Low-Power GigaBit Transceiver (lpGBT) chip which enables emulation of the detector front-ends for integration tests. This paper presents the GRM hardware design and its testing.

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Hardware design of the generic rear transition module for the global trigger system of the ATLAS phase II upgrade

Cited by 2 publications

References 4 publications

Hardware Optimization and System Design of Elliptic Curve Encryption Algorithm Based on FPGA

Hardware Optimization and System Design of Elliptic Curve Encryption Algorithm Based on FPGA

Hardware design and testing of the generic rear transition module for the global trigger subsystem of ATLAS Phase-II Upgrade

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