Hardware Design of Intra Prediction Angular Mode Decision for HEVC Encoder

Abstract

In this paper, we propose a hardware design of intra prediction angular mode decision for HEVC encoder. The intra prediction of HEVC includes a total of 35 modes and has better coding performance than H.264/AVC. However, high computational complexity and computation time are required to process all 35 modes. Therefore, this paper proposes a hardware structure using an efficient angular mode decision algorithm by the simple operation using the difference of the original pixel and its position. The hardware architecture of this paper reduces computation time by parallel processing from 4x4 block size to 64x64 block size. In this paper, we use a minimized arithmetic unit by determining the angular mode by predicting the direction through a simple operation unlike the existing structure. The proposed hardware architecture was designed using Verilog HDL, implemented on a 65nm technology, synthesized with Synopsys design compiler. Synthesized gate count amounted to 14.9K and the maximum operating frequency at 2GHz.