Hardware design of a Binary Integer Decimal-based floating-point adder

Abstract

Because of the growing importance of decimal floating-point (DFP) arithmetic, specifications for it are included in the IEEE Draft Standard for Floating-point Arithmetic (IEEE P754). In this paper, we present a novel algorithm and hardware design for a DFP adder. The adder performs addition and subtraction on 64-bit operands that use the IEEE P754 binary encoding of DFP numbers, widely known as the Binary Integer Decimal (BID) encoding. The BID adder uses a novel hardware component for decimal digit counting and an enhanced version of a previously published BID rounding unit. By adding more sophisticated control, operations are performed with variable latency to optimize for common cases. We show that a BID-based DFP adder design can be achieved with a modest area increase compared to a single 2-stage pipelined 64-bit fixed-point multiplier. Over 70% of the BID adder's area is due the 64-bit fixed-point multiplier, which can be shared with a binary floating-point multiplier and hardware for other DFP operations. To our knowledge, this is the first hardware design for adding and subtracting IEEE P754 BID-encoded DFP numbers.

A FPGA IEEE-754-2008 decimal64 Floating-Point adder/subtractor

“…The hardware implementation includes the IBM Power6 and Z10 processors whos has hardware acceleration for decimal floating point [22] [23], and the Binary Integer Decimal (BID) implementation in 65nm and Virtex 5. [9,10] The proposed FPGA implementation is more than one order of magnitude faster than the software implementation. The hardware acceleration present in Z10 and Power 6 is faster than a single Virtex 5 core.…”

“…Several hardware designs were synthesized using other platforms than FPGA [10], this is why it is believed that it can be one of the first implementation on FPGA for addition/subtraction using decimal64 encoding. A recent work [9] presents a DFP adder for FPGA but using Binary Integer Decimal (BID) encoding, whose results will be used in our comparisons.…”

Are Ieee 754 32-Bit and 64-Bit Binary Floating-Point Accurate Enough?

“…All the research papers consulted in this research [5,[19][20][21]. [3][4][14][15]18,[21][22][23][24][28][29] did not provide direct relationship between the width of fraction and the width of available unsigned registers in determining the upper bound of accuracy of decimal fraction computed within binary floating-point. We establish the direct relation-ships between y fraction bits and z bit of unsigned integral registers in the statement (8) and (9) On the reverse direction z bit unsigned integral register will be capable of representing decimal-digits fraction accurately without sophisticated algorithm.…”

Decimal Floating Point Number System

“…To align the significands for addition in numbers encoded in BID [27], we use a multiplier to multiply by 10 exp_diff . Rounding of BID encoded numbers poses a similar challenge [28,29].…”