Hardware Design and Simulation in VAL/VHDL

Augustin, Larry M.; Luckham, David C.; Gennart, Benoit A.; Huh, Youm; Stanculescu, Alec G.

doi:10.1007/978-1-4615-4042-7

Cited by 19 publications

(7 citation statements)

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“…This differs from vspec's purpose of representing requirements and design decisions at high levels of abstraction. Augustin et al's val [21] is another attempt to annotate vhdl. The purpose of a val annotation to a vhdl description is to document the design for verification.…”

Section: Related Workmentioning

confidence: 99%

A brief summary of VSPEC

Alexander

Rangarajan

Baraona

1999

FM’99 — Formal Methods

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Abstract. This paper provides an overview of the vspec behavioral interface specification language for vhdl. Although operational specification language such as vhdl provide exceptional specification capabilities, at the systems requirements level the operational style is a hindrance. vspec provides vhdl users with a declarative mechanism for defining functional requirements and performance constraints. In the tradition of behavioral interface specification languages, vspec adds clauses to the vhdl entity construct allowing axiomatic specification of functional requirements. Because system constraints play an ever increasing role in systems design, vspec also provides performance constraint specification capability. This paper presents the basics of vspec, its semantics, semantic analysis, and briefly describes current and future applications.

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Section: Related Workmentioning

confidence: 99%

A brief summary of VSPEC

Alexander

Rangarajan

Baraona

1999

FM’99 — Formal Methods

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“…We have chosen the symbol "//|" similarly to that of VAL (VHDL Annotation Language) [1] where "--|" is used as a symbol for this kind of pseudo-comment.…”

Section: Critique Of the Java Conceptmentioning

confidence: 99%

“…They could also be very useful coordinates for an OO-extension of VHDL as -this language already has an adequate basis mechanism in the form of the principle of separation in entity and architecture, -there are analogies between VHDL structure descriptions and the object-oriented approach [7] and -in the case of VAL (VHDL Annotation Language), a number of decisions have already taken it along the path towards constraint handling (assume, assert, finally, eventually, sometime) [1]. A concept of contract honoring (see above) can be constructed on these developments.…”

Section: Conclusion Relating To An Ooextension Of Vhdlmentioning

confidence: 99%

Enhanced reuse and teamwork capabilities for an object-oriented extension of VHDL

Mrva¹

Proceedings Design, Automation and Test in Europe

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“…Because of the increasing level of complexity, it is becoming more and more time-consuming for a designer to obtain an acceptable level of confidence in the correctness of the design specification. This problem can be alleviated by a tighter integration of evaluation and analysis methods into the design environment [1] [5]. These methods facilitate the task of interpreting the detailed simulation results.…”

Section: Introductionmentioning

confidence: 99%

“…In [1] the VAL language is proposed as an annotation language for VHDL. It extends the language with a small set of new constructs for abstract specification.…”

Section: Introductionmentioning

confidence: 99%