Hardware Design and Implementation of Adaptive Multiple Transforms for the Versatile Video Coding Standard

Kammoun, Ahmed; Hamidouche, Wassim; Belghith, Fatma; Nezan, Jean-François; Nouri, Mohammad

doi:10.1109/tce.2018.2875528

Cited by 32 publications

(40 citation statements)

References 13 publications

(26 reference statements)

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“…Practically, up to 80.5% of area can be reduced compared to [11] and up to 76.7% compared to [6]. In term of ALMs, we provide 92.7% reduction compared to implementation proposed by Kammoun et al in [10]. However, currently, no implementation have been found for the IDCT-II of order 64.…”

Section: Resultsmentioning

confidence: 88%

“…Most studies focus on earlier version of VVC, and there are few ASIC-based designs for the VVC MTS. For comparison, Table 3 lists the key performance of state-of-the-art ASIC and FPGA-based works, including the VVC-MTS related works [11,9,6,10]. Gate count is the logical calculation part and it can be seen from Table 3 that compared with implementations of Fan et al [11] and Mert et al [6], our solution has obvious advantages.…”

Section: Resultsmentioning

confidence: 99%

“…However, currently, no implementation have been found for the IDCT-II of order 64. Although, [11] and [10] supports 2D for all transform types, the transform could be achieved only up to the 32×32 block size.…”

Section: Resultsmentioning

confidence: 99%

“…Although the work in [7] supports all VVC transform types, it does not support blocks of size 64 × 64 which significantly increases the complexity. Kammoun et al [10] proposed another hardware implementation for the same transform types and sizes. It implements the transformation using IP cores multiplier taking advantage of DSPs of the FPGA device.…”

Section: Existing Hardware Implementationsmentioning

confidence: 99%

“…It implements the transformation using IP cores multiplier taking advantage of DSPs of the FPGA device. The work in [10] proposes a 2-D hardware implementation. Although it includes 2-D implementation, blocks of sizes 64 × 64 are also not supported.…”

Section: Existing Hardware Implementationsmentioning

confidence: 99%

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Lightweight Hardware Implementation of VVC Transform Block for ASIC Decoder

Farhat

Hamidouche

Grill

et al. 2020

ICASSP 2020 - 2020 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP)

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Versatile Video Coding (VVC) is the next generation video coding standard expected by the end of 2020. Compared to its predecessor, VVC introduces new coding tools to make compression more efficient at the expense of higher computational complexity. This rises a need to design an efficient and optimised implementation especially for embedded platforms with limited memory and logic resources. One of the newly introduced tools in VVC is the Multiple Transform Selection (MTS). This latter involves three Discrete Cosine Transform (DCT)/Discrete Sine Transform (DST) types with larger and rectangular transform blocks. In this paper, an efficient hardware implementation of all DCT/DST transform types and sizes is proposed. The proposed design uses 32 multipliers in a pipelined architecture which targets an ASIC platform. It consists in a multi-standard architecture that supports the transform block of recent MPEG standards including AVC, HEVC and VVC. The architecture is optimized and removes unnecessary complexities found in other proposed architectures by using regular multipliers instead of multiple constant multipliers. The synthesized results show that the proposed method which sustain a constant throughput of two pixels/cycle and constant latency for all block sizes can reach an operational frequency of 600 Mhz enabling to decode in real-time 4K videos at 48 fps.

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Section: Resultsmentioning

confidence: 88%