Hardware Design and Analysis of Block Cipher Components

Abstract

This paper describes the efficient implementation of Maximum Distance Separable (MDS) mappings and Substitution-boxes (S-boxes) in gate-level hardware for application to Substitution-Permutation Network (SPN) block cipher design. Different implementations of parameterized MDS mappings and S-boxes are evaluated using gate count as the space complexity measure and gate levels traversed as the time complexity measure. On this basis, a method to optimize MDS codes for hardware is introduced by considering the complexity analysis of bit parallel multipliers. We also provide a general architecture to implement any invertible S-box which has low space and time complexities. As an example, two efficient implementations of Rijndael, the Advanced Encryption Standard (AES), are considered to examine the different tradeoffs between speed and time.

Hardware Performance Characterization of Block Cipher Structures

“…To calculate the gate count and number of gate layers per round, we consider the construction of the combinational circuits of the round structure with S-box and MDS mapping components which can produce high efficiencies in hardware. The hardware design and optimization of these components are described in [6]. The detailed data used in the complexity estimation is presented in the Appendix.…”

“…In hardware, the complexity of S-boxes are evaluated through the simplification results deduced from an encoder-switch-decoder model [6]. In this model, S-boxes are composed of low complexity gates (ANDs, ORs, and NOTs).…”

“…A 4 × 4 S-box can be implemented using 50 gates and produces a delay of 6 gate layers; an 8 × 8 S-box can be implemented using 806 gates and produces a delay of 11 gate layers. Involution MDS codes [4] are found by searching Hadamard matrices and have been optimized for hardware [6]. MDS codes are composed of XORs.…”

“…A performance comparison is made between different parameterized cases of 128-bit block ciphers in relation to security requirements. In the analysis, the hardware complexities of S-boxes and MDS mappings are based on the upper bounds of the minimum hardware complexity deduced in [6]. For a general invertible S-box, the upper bounds of the gate count and delay are obtained from the logic minimization of a hardware-efficient S-box model; for an MDS mapping, the upper bounds of the gate count and delay are obtained by searching MDS candidates for an optimal one when implemented by bit-parallel multipliers.…”

“…Hence, the structures discussed in this paper are constructed with optimized components to produce high efficiencies in their categories. A conventional evaluation approach is taken in [6] with the space complexity evaluated by the number of bit-wise invertors and 2-input gates and the time complexity evaluated by the number of traversed layers in the gate network. In this paper, a weight is associated with different types of gates to distinguish their discrepancies in hardware cost.…”