Hardware-compressive 2-D fiber optic delay line architecture for time steering of phased-array antennas

Abstract

The requirements for true time steering of phased array antennas are reviewed, and the resulting delay line hardware requirements are discussed. Two hardware-compressive fiber optic delay line architectures are then briefly described and quantitatively compared. The basics of phased array antenna partition are then presented. Based on these principles a delay-compressive and element-compressive 2-D fiber optic delay line architecture is described, and its basic characteristics and capabilities are discussed.

The Design of an Optical Time Steered Antenna Based on a New Integrated True Time Delay Unit

“…Regarding the number M of quantization bits, it must be noted that a high value for M , although reducing the time delay quantization error, also increases hardware complexity and losses. In fact, larger quantization levels require larger numbers of delay stages, thus increasing the total losses and hardware complexity of each time shifter, as discussed in [25,26].…”

A Flexible Integrated Photonic True Time Delay Phaser for Phased Array Antennas

“…Accordingly we will compare our TTDU to PaDeL architectures, since the differences among the main SDL schemes have been already widely discussed [33].…”

“…Leaving this out of consideration, we use the figure of merit proposed in [33] for the main SDL architectures: it is based on the number of lasers, fibers and switches employed for each TS. Accordingly, for a B bits TS, the figure of merit related to the PaDeL scheme [2,14] is C P aDeL = 2 B+1 , since 2 B lasers and 2 B fibers are employed [33].…”

“…Accordingly, for a B bits TS, the figure of merit related to the PaDeL scheme [2,14] is C P aDeL = 2 B+1 , since 2 B lasers and 2 B fibers are employed [33]. The hardware complexity figure of merit for the proposed scheme, C TPH , can be evaluated similarly to the PaDeL case as the sum of the four following terms: the number of lasers, equal to 1, the number of external delay lines, the number of realized switches, equal to 2 B , and the number of exploited waveguides, equal to 0.5 (N IN +N OUT ), N IN and N OUT being the number of TTDU inputs and outputs exploited, respectively.…”

Hardware Demonstration of Extremely Compact Optical True Time Delay Device for Wideband Electronically Steered Antennas

“…Fiber-or waveguide-based approaches switch beams among waveguide paths of varying lengths [2]- [6] or use multiple wavelengths and dispersion to create relative delays [7]- [10]. Fiber lengths can be arbitrarily long and have low loss but the lengths are difficult to control accurately.…”