Hardware compressed main memory: operating system support and performance evaluation

Abali, Bülent; Shen, Xiaowei; Franke, Hubertus; Poff, Dan; Smith, T. B.

doi:10.1109/12.966496

Cited by 18 publications

(12 citation statements)

References 7 publications

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“…Data compression is used to reduce storage requirements, bus bandwidth, and energy consumption [10]- [19]. Using a hardware compressor enables faster compression/ decompression, and this has been achieved by various techniques [10], [20]- [22]. Our work is different from these prior efforts as we give the task of the management of the compressed data blocks to the compiler.…”

Section: Related Workmentioning

confidence: 94%

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Using Data Compression for Increasing Memory System Utilization

Öztürk

Kandemir

Irwin

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-The memory system presents one of the critical challenges in embedded system design and optimization. This is mainly due to the ever-increasing code complexity of embedded applications and the exponential increase seen in the amount of data they manipulate. The memory bottleneck is even more important for multiprocessor-system-on-a-chip (MPSoC) architectures due to the high cost of off-chip memory accesses in terms of both energy and performance. As a result, reducing the memory-space occupancy of embedded applications is very important and will be even more important in the next decade. While it is true that the on-chip memory capacity of embedded systems is continuously increasing, the increases in the complexity of embedded applications and the sizes of the data sets they process are far greater. Motivated by this observation, this paper presents and evaluates a compilerdriven approach to data compression for reducing memoryspace occupancy. Our goal is to study how automated compiler support can help in deciding the set of data elements to compress/ decompress and the points during execution at which these compressions/decompressions should be performed. We first study this problem in the context of single-core systems and then extend it to MPSoCs where we schedule compressions and decompressions intelligently such that they do not conflict with application execution as much as possible. Particularly, in MPSoCs, one needs to decide which processors should participate in the compression and decompression activities at any given point during the course of execution. We propose both static and dynamic algorithms for this purpose. In the static scheme, the processors are divided into two groups: those performing compression/decompression and those executing the application, and this grouping is maintained throughout the execution of the application. In the dynamic scheme, on the other hand, the execution starts with some grouping but this grouping can change during the course of execution, depending on the dynamic variations in the data access pattern. Our experimental results show that, in a single-core system, the proposed approach reduces maximum memory occupancy by 47.9% and average memory occupancy by 48.3% when averaged over all the benchmarks. Our results also indicate that, in an MPSoC, the average energy saving is 12.7% when all eight benchmarks are considered. While compressions and decompressions and related bookkeeping activities take extra cycles and memory space and consume additional energy, we found that the improve-

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Section: Related Workmentioning

confidence: 94%

“…Very long instruction word processors are also considered in compression-related work [5]- [9]. Data compression is used to reduce storage requirements, bus bandwidth, and energy consumption [10]- [19]. Using a hardware compressor enables faster compression/ decompression, and this has been achieved by various techniques [10], [20]- [22].…”

Section: Related Workmentioning

confidence: 99%

Using Data Compression for Increasing Memory System Utilization

Öztürk

Kandemir

Irwin

2009

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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“…In [18] and [1] the MTX technology and the operating system modifications needed to run on top of a compression hardware are described. In [5] a performance evaluation with promising results over different workloads is presented. However, this project has not been successful, probably because of the cost of the specialized hardware versus the cost of memory chips.…”

Section: Related Workmentioning

confidence: 98%

Improving disk bandwidth-bound applications through main memory compression

Beltrán

Torres

Ayguadé

2007

Proceedings of the 2007 Workshop on MEmory Performance: DEaling With Applications, Systems and Architecture

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The objective of main memory compression techniques is to reduce the in-memory data size to virtually enlarge the available memory on the system. The main benefit of this technique is the reduction of slow disk I/O operations, thus improving data access latency and saving disk I/O bandwidth. On the other hand, its main drawback is the large amount of CPU power needed by the computationally expensive compression algorithms, that make it unsuitable for medium to large CPU intensive applications.With the proliferation of multicore processors and multiprocessor systems, the amount of available CPU power is growing at a fast rate. In this scenario, the number of applications that can transparently benefit from main memory compression can be expanded. Now, not only, single threaded applications, bounded by disk latencies, but also multithreaded ones, bounded by the disk bandwidth can benefit from main memory compression techniques. In this paper we implement and evaluate in the Linux OS a full SMP capable main memory compression subsystem that takes advantage of a current multicore and multiprocessor system to increase the performance of bandwidth sensitive applications like the SPECweb2005 benchmark with promising results.

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“…Figure 5 shows the memory requirement curves for these 55 benchmarks. 2 While the worst-case requirement is close to 1GB, most of the applications require much less than 0.5GB of memory capacity. However, the system must be provisioned with enough capacity to run the worst-case benchmark in the suite.…”

Section: Motivationmentioning

confidence: 99%

Morphable memory system

Qureshi

Franceschini

Lastras-Montaño

et al. 2010

Proceedings of the 37th Annual International Symposium on Computer Architecture

126

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Phase Change Memory (PCM) is emerging as a scalable and powerefficient technology to architect future main memory systems. The scalability of PCM is enhanced by the property that PCM devices can store multiple bits per cell. While such Multi-Level Cell (MLC) devices can offer high density, this benefit comes at the expense of increased read latency, which can cause significant performance degradation. This paper proposes Morphable Memory System (MMS), a robust architecture for efficiently incorporating MLC PCM devices in main memory. MMS is based on observation that memory requirement varies between workloads, and systems are typically over-provisioned in terms of memory capacity. So, during a phase of low memory usage, some of the MLC devices can be operated at fewer bits per cell to obtain lower latency. When the workload requires full memory capacity, these devices can be restored to high density MLC operation to have full main-memory capacity. We provide the runtime monitors, the hardware-OS interface, and the detailed mechanism for implementing MMS. Our evaluations on an 8-core 8GB MLC PCM-based system show that MMS provides, on average, low latency access for 95% of all memory requests, thereby improving overall system performance by 40%.

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Hardware compressed main memory: operating system support and performance evaluation

Cited by 18 publications

References 7 publications

Using Data Compression for Increasing Memory System Utilization

Using Data Compression for Increasing Memory System Utilization

Improving disk bandwidth-bound applications through main memory compression

Morphable memory system

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