Hardware-based data value and address trace filtering techniques

ACM Trans. Embed. Comput. Syst.

2013

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________________________________________________________________________Capturing program and data traces during program execution unobtrusively on-the-fly is crucial in debugging and testing of cyber-physical systems. However, tracing a complete program unobtrusively is often costprohibitive, requiring large on-chip trace buffers and wide trace ports. This paper describes a new hardwarebased load data value filtering technique called Cache First-access Tracking. Coupled with an effective variable encoding scheme, this technique achieves a significant reduction of load data value traces, from 5.86 to 56.39 times depending on the data cache size, thus enabling cost-effective unobtrusive on-the-fly tracing and debugging.

Section: Cache First-access Tracking Mechanismmentioning

confidence: 99%

Hardware-Based Load Value Trace Filtering for On-the-Fly Debugging

Uzelac¹,

ACM Trans. Embed. Comput. Syst.

2013

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“…ARM's new Embedded Trace Macrocell version four (ETMv4) proposed for ARMv7 ISA employs branch predictor to reduce the control-flow trace port bandwidth, reporting $0.35 bits per instruction [14]. For load value traces, Uzelac and Milenkovic [15,16] introduced cache first-access tracking mechanism (c-fiat) that reduces the trace size between 5.8 and 56 times, depending on the cache size. However, these techniques have been demonstrated for uniprocessors only.…”

Section: Introductionmentioning

confidence: 99%

“…11 12 13 14 15 16 17 18 19 20 21 22 23 24 length (field) [bits]CDF for bCnt, |diffTA|, & diffCC: Cumulative distribution function of the minimum length for bCnt, |diffTA|, and diffCC fields.…”

mentioning

confidence: 99%

mcfTRaptor: Toward unobtrusive on-the-fly control-flow tracing in multicores

Tewar

Myers

Journal of Systems Architecture

2015

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a b s t r a c tSoftware testing and debugging has become the most critical aspect of the development of modern embedded systems, mainly driven by growing software and hardware complexity, increasing integration, and tightening time-to-market deadlines. Software developers increasingly rely on on-chip trace and debug infrastructure to locate software bugs faster. However, the existing infrastructure offers limited visibility or relies on hefty on-chip buffers and wide trace ports that significantly increase system cost. This paper introduces a new technique called mcfTRaptor for capturing and compressing functional and time-stamped control-flow traces on-the-fly in modern multicore systems. It relies on private on-chip predictor structures and corresponding software modules in the debugger to significantly reduce the number of events that needs to be streamed out of the target platform. Our experimental evaluation explores the effectiveness of mcfTRaptor as a function of the number of cores, encoding mechanisms, and predictor configurations. When compared to the Nexus-like control-flow tracing, mcfTRaptor reduces the trace port bandwidth in the range from 14 to 23.8 times for functional traces and 10.8-18.6 times for time-stamped traces.

“…Capturing and compression of data traces is thus out of the scope of this paper. More information on capturing and filtering of data traces in real-time can be found elsewhere [10].…”

Section: Introductionmentioning

confidence: 99%

Using Branch Predictors and Variable Encoding for On-the-Fly Program Tracing

Uzelac¹,

Milenković³

et al. 2014

IEEE Trans. Comput.

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Abstract-Unobtrusive capturing of program execution traces in real-time is crucial for debugging many embedded systems. However, tracing even limited program segments is often cost-prohibitive, requiring wide trace ports and large on-chip trace buffers. This paper introduces a new cost-effective technique for capturing and compressing program execution traces on-thefly. It relies on branch predictor-like structures in the trace module and corresponding software modules in the debugger to significantly reduce the number of events that need to be streamed out of the target system. Coupled with an effective variable encoding scheme that adapts to changing program patterns, our technique requires merely 0.029 bits per instruction of trace port bandwidth, providing a 34-fold improvement over the commercial state-of-the-art and a five-fold improvement over academic proposals, at the low cost of under 5,000 logic gates.