Hardware-Based Comparative Analysis of Multilevel Inverter Topologies for Integrated Motor Drives Considering Overload Operation

Abstract

With today's demand for increased industrial process automation a trend towards Integrated Motor Drives (IMDs) has evolved allowing a low complexity and compact installation of the drive system. Especially servo applications with high short-term overload requirements (e.g., three times the nominal current for several seconds) are a thermal challenge for the power electronics. Consequently, high efficiencies and power densities are key requirements of these motor-integrated Variable Speed Drives (VSDs). Multi-Level (ML) inverter topologies allow small LC output filter designs and benefit from utilizing low-voltage semiconductors with superior conduction and switching performance, and thus represent an interesting approach for future IMDs. In this work an experimental comparison between three different 800 V DC link supplied drive systems is presented, namely between a 3L Flying Capacitor Converter (3L-FCC) (employing 650 V GaN HEMTs), a 7L Flying Capacitor Converter (7L-FCC) (using 200 V Si MOSFETs) and its promising alternative, a 7L Hybrid Active Neutral-Point Clamped Converter (7L-HANPC) (using both, 650 V GaN HEMTs and 200 V Si MOSFETs). All three systems are realized as hardware demonstrators for the same specifications, i.e., for integration into a Permanent Magnet Synchronous Motor (PMSM) with a case temperature of 90 • C, 7.5 kW nominal output power at >99% efficiency and a short-term overload capability of three times the nominal current for 3 s. Thereby, the efficiencies and the thermally critical overload capability are experimentally verified. Overall, the 3L-FCC shows the best performance trade-off with lowest complexity and/or highest reliability and minimal control effort.

Comparative Evaluation of Three-Phase Three-Level Flying Capacitor and Stacked Polyphase Bridge GaN Inverter Systems for Integrated Motor Drives

“…Power Transistors GaN Systems GS66516T (650 V, 25 mΩ), 2 × parallel per position; 27.2 mm 2 device chip area [48]…”

“…During the overload operation, an equal stress increase is expected for the key components of both topologies. This characteristic is quantified in [48] (with temperature-critical semiconductors in the forefront) and shows the utilization of the maximum allowed semiconductor junction temperature after a 3 s standstill overload operation with 45 A peak current in one phase. The junction temperature evaluation considers a transient dynamic thermal model with non-ideal heat spreading in the baseplate, on which the PCB with the semiconductors is mounted [5].…”