Hardware based analysis of RFID anti-collision protocols based on the standard EPCglobal Class-1 Generation-2

Abstract

Radio Frequency Identification (RFID) technology is undergoing a remarkable development in the last few years. In this technology, identification information is exchanged between two devices: readers and tags. If two tags attempt to transmit simultaneously, a collision is produced. This phenomena, known as the tag collision problem, is becoming increasingly important, since it leads to an increase in the number of reader transmitted bits and identification delay, in addition to a wastage of energy and bandwidth. In this context, protocols based on the EPCglobal Class-1 Generation-2 (EPC C1G2) standard arbitrate collisions by adjusting the transmission frame size. The standard presents an uncertainty in the selection of the frame size, since it does not specify the exact value. This has led to many different alternatives. This paper presents a hardware analysis of the most relevant anti-collision protocols which deal with this uncertainty. The focus of this analysis is to design and evaluate with VHDL the tag's chip design in order to extract the number clock cycles a tag employs to be identified.

A constructive Steiner graph matching for Radio frequency identification device tag detection in wireless and internet of things environment

“…Arjona et al proposed techniques based on the EPCglobal Class‐1 Generation‐2 (EPC C1G2) standard to resolve collisions by changing the transmission frame size 18 . Arjona et al conducted a hardware analysis of the most essential anti‐collision protocols for dealing with this uncertainty.…”

“…Arjona et al conducted a hardware analysis of the most essential anti‐collision protocols for dealing with this uncertainty. This analysis focuses on designing and evaluating the tag chip layout in VHDL to determine the number of clock cycles the tag uses for identification 20 . However, for these algorithms to be compatible with existing hardware running on EPC Gen‐2 platforms, significant modifications to existing protocol structures would be required, which would be prohibitively expensive.…”

“…17 Arjona et al proposed techniques based on the EPCglobal Class-1 Generation-2 (EPC C1G2) standard to resolve collisions by changing the transmission frame size. 18 Arjona et al conducted a hardware analysis of the most essential anti-collision protocols for dealing with this uncertainty. This analysis focuses on designing and evaluating the tag chip layout in VHDL to determine the number of clock cycles the tag uses for identification.…”

“…This analysis focuses on designing and evaluating the tag chip layout in VHDL to determine the number of clock cycles the tag uses for identification. 20 However, for these algorithms to be compatible with existing hardware running on EPC Gen-2 platforms, significant modifications to existing protocol structures would be required, which would be prohibitively expensive. Although C1G2 uses an efficient anti-collision algorithm, as the number of tags increases, so does the probability of collision, which may result in decreased system efficiency and a longer identification time.…”

“…The Class 1 Generation 2 (C1G2) algorithm, 18 also known as the anti‐collision algorithm in RFID systems, is designed to handle multiple tags that communicate with a reader simultaneously. C1G2 employs a frame‐based communication protocol wherein tags respond to reader queries within predefined frames.…”