Hardware atomicity for reliable software speculation

Neelakantam, Naveen; Rajwar, Ravi; Srinivas, Suresh; Srinivasan, Uma; Zilles, Craig

doi:10.1145/1250662.1250684

Cited by 69 publications

(12 citation statements)

References 16 publications

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“…Most software techniques focus on loop or region based parallelization [1]- [5] not improving inherently sequential code. Hardware-based speculation support has been used to enable unsafe optimization of sequential code [6]- [9]. Fast track supports speculative program optimization in software, and because of its software nature, it provides a programming interface for invoking and managing the speculation system.…”

Section: If (Fasttrack ())mentioning

confidence: 99%

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Fast Track: A Software System for Speculative Program Optimization

Kelsey

Bai

Ding

et al. 2009

2009 International Symposium on Code Generation and Optimization

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Abstract-Fast track is a software speculation system that enables unsafe optimization of sequential code. It speculatively runs optimized code to improve performance and then checks the correctness of the speculative code by running the original program on multiple processors.We present the interface design and system implementation for Fast Track. It lets a programmer or a profiling tool mark fast-track code regions and uses a run-time system to manage the parallel execution of the speculative process and its checking processes and ensures the correct display of program outputs. The core of the run-time system is a novel concurrent algorithm that balances exploitable parallelism and available processors when the fast track is too slow or too fast. The programming interface closely affects the run-time support. Our system permits both explicit and implicit end markers for speculatively optimized code regions as well as extensions that allow the use of multiple tracks and user defined correctness checking. We discuss the possible uses of speculative optimization and demonstrate the effectiveness of our prototype system by examples of unsafe semantic optimization and a general system for fast memory-safety checking, which is able to reduce the checking time by factors between 2 and 7 for large sequential code on a 8-CPU system.

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Section: If (Fasttrack ())mentioning

confidence: 99%

“…Unlike fast track, run-ahead threads accelerate rather than parallelize the execution of sequential code. A third, more recent idea is speculative optimization at fine granularity, which does not yet make use of multiple processors [9]. All of these techniques require modification to existing hardware.…”

Section: Related Workmentioning

confidence: 99%

Fast Track: A Software System for Speculative Program Optimization

Kelsey

Bai

Ding

et al. 2009

2009 International Symposium on Code Generation and Optimization

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“…TM support (7) or hardware atomicity support proposed in (12), if available, could also be used in conjunction with our efficient addressing scheme to enforce atomicity. However, our CSC scheme, in comparison with TM, does not require support for checkpointing (9) or conflict detection since there is no rollback or re-execution.…”

Section: Tm For Atomicitymentioning

confidence: 99%

Runtime monitoring on multicores via OASES

Nagarajan

Gupta

2009

SIGOPS Oper. Syst. Rev.

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Runtime monitoring support serves as a foundation for the important tasks of providing security, performing debugging, and improving performance of applications. Often runtime monitoring requires the maintenance of information associated with each of the application's original memory location, which is held in corresponding shadow memory locations. Unfortunately, existing robust shadow memory implementations are inefficient. In this paper, we present OASES: OS and Architectural Support for Efficient Shadow memory implementation for multicores that is also robust. A combination of operating system support (in the form of coupled allocation of memory pages used by the application and associated shadow memory pages) and architectural support (in the form of ISA support and exposed cache events) is proposed. Our page allocation policy enables fast translation of original addresses into corresponding shadow memory addresses; thus allowing implicit addressing of shadow memory. By exposing the cache events to the software, we ensure in software that the shadow memory instructions execute atomically with their corresponding original memory instructions. Our experiments show that the overheads of runtime monitoring tasks are significantly reduced in comparison to previous software implementations.

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“…There has also been recent work leveraging transactional hardware primitives in support of optimizations that require efficient conflict detection and/or checkpointing [23,33]. In contrast to the work presented here, which focuses on reducing the overheads of transactional runtime systems, these papers explore compiler and runtime optimizations that leverage TM hardware to optimize applications regardless of whether they may have been written to use transactions.…”

Section: Related Workmentioning

confidence: 99%

Compiler and runtime techniques for software transactional memory optimization

Michael

Praun

et al. 2008

Concurrency and Computation

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SUMMARYSoftware transactional memory (STM) systems are an attractive environment to evaluate optimistic concurrency. We describe our experience of supporting and optimizing an STM system at both the managed runtime and compiler levels. We describe the design policies of our STM system, and the statistics collected by the runtime to identify performance bottlenecks and guide tuning decisions. We present initial work on supporting automatic instrumentation of STM primitives for C/C++ and Java programs in the IBM XL compiler and J9 JVM. We evaluate and discuss the performance of several transactional programs running on our system.

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Hardware atomicity for reliable software speculation

Cited by 69 publications

References 16 publications

Fast Track: A Software System for Speculative Program Optimization

Fast Track: A Software System for Speculative Program Optimization

Runtime monitoring on multicores via OASES

Compiler and runtime techniques for software transactional memory optimization

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