Hardware-assisted simulated annealing with application for fast FPGA placement

Abstract

To truly exploit FPGAs for rapid turn-around development and prototyping, placement times must be reduced to seconds; latebound, reconfigurable computing applications may demand placement times as short as microseconds. In this paper, we show how a systolic structure can accelerate placement by assigning one processing element to each possible location for an FPGA LUT from a design netlist. We demonstrate that our technique approaches the same quality point as traditional simulated annealing as measured by a simple linear wirelength metric. Experimental results look ahead to compare quality against VPR's fast placer when considering the minimum channel width required to route as the primary optimization criteria. Preliminary results from an FPGA implementation show the feasibility of accelerating simulated annealing by three orders of magnitude using this approach. This means we can place the largest design in the University of Toronto's "FPGA Placement and Routing Challenge" in around 4ms.

New timing and routability driven placement algorithms for FPGA synthesis

“…One is to enable SA only when the temperature is low, like Frontier, a system developed by Tessier to achieve highly routable and high-performance layouts [15]. Another one is utilizing hardware to assist SA, like the systolic structure proposed by Wrighton et al in [17].…”

“…Preferably, we would like to compute Satx,y in such a way that the more empty blocks CLBx,y is adjacent to, the smaller Satx,y becomes. This is taken into account by introducing Nun in Equation (17). On the other hand, we want to avoid placing a large number of unused blocks in the same region in order to reduce congestion.This is why we use allev/2 in Equation (17) when CLBx,y is not occupied.…”

GPU Approach to FPGA placement based on star+

“…In particular, we propose an algorithm, inspired by the systolic-array structure in [6], that allows many independent moves to be considered simultaneously, greatly increasing the amount of parallelism exposed to the underlying GPU architecture (as compared to the work in [4]). We also organize the parallelism in our approach so that each logic block considered for swapping is assigned to a single GPU thread, ensuring that every possible thread is doing useful work.…”

Multilevel Optimization for Large-Scale Hierarchical FPGA Placement

“…There are other papers focusing on FPGA CAD such as [8] published in Chinese top journal. However, existing fast FPGA placement tools [9][10] , based on conventional simulatedannealing scheme, can only treat medium-scale circuits whereas multilevel optimization method can efficiently yield good quality-time tradeoff results for large-scale circuits.…”