Hardware Architecture of CABAC Binary Arithmetic Encoder for HEVC Encoder

Abstract

This paper proposes an efficient binary arithmetic encoder hardware architecture for CABAC (Context-based Adaptive Binary Arithmetic Coding) encoding. CABAC is an entropy coding method that is used in HEVC standard. Entropy coding removes statistical redundancy and supports a high compression ratio of images. However, the binary arithmetic encoder causes a delay in real time processing and parallel processing is difficult because of the high dependency between data. The operation of the proposed CABAC BAE hardware structure is to separate the renormalization and process the conventional iterative algorithm in parallel. The new scheme was designed as a four-stage pipeline structure that can reduce critical path optimally. The proposed CABAC BAE hardware architecture was designed with Verilog HDL and implemented in 65nm technology. Its gate count is 5.68K and maximum clock frequency is 1.11GHz. It processes the 2 bins per clock cycle. Maximum processing speed increased by 22% from existing hardware architectures. And Gate count has been reduced by 31%.

Context-based Adaptive Binary Arithmetic Coding (CABAC): Design and Implementation Using a Multi-Symbol Binary Arithmetic Coder

“…In [15], the author utilized a dedicated core for every bin that is utilized and the utilized bin is processed for every cycle. To improve speed, the author introduced two concurrent four-stage pipelined binary arithmetic encoding cores in [16]. They used a LUT to generate bitstream in order to minimize operating time.…”

High-Throughput Architecture of HEVC CABAC Binary Arithmetic Encoder

“…[4]. In this paper, we propose a hardware design of a CABAC binary arithmetic encoder with high throughput by applying a four-stage pipeline structure that can operate optimally by separating delayed sections in the computation process -this paper is an elaborate version of our previous work [5]. In order to optimize critical path and output the variable bitstream in one cycle, the information bit is generated and output simply through the LUT.…”