Hardware aging-based software metering

Dabiri,; Potkonjak,

doi:10.1109/date.2009.5090709

Cited by 17 publications

(12 citation statements)

References 6 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Gate level characterization (GLC) under the impact of process variation has been assumed as a key step in many hardware security applications [10] [20]. The basic approaches which have been proposed [3][11] [19] characterize the manifestational properties of each gate by measuring the overall properties of the entire IC.…”

Section: Related Workmentioning

confidence: 99%

Robust passive hardware metering

Wei¹,

Nahapetian²,

Potkonjak³

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

Current hardware metering techniques, which use manifestational properties of gates for ID extraction, are weakened by the non-uniform effects of aging in conjunction with variations in temperature and supply voltage. As an integrated circuit (IC) ages, the manifestational properties of the gates change, and thus the ID used for hardware metering can not be valid over time. Additionally, the previous approaches require large amounts of costly measurements and often are difficult to scale to large designs.We resolve the deleterious effects of aging by going to the physical level and primarily targeting the characterization of threshold voltage. Although threshold voltage is modified with aging, we can recover its original value for use as the IC identifier. Another key aspect of our approach involves using IC segmentation for gate-level characterization. This results in a cost effective approach by limiting measurements, and has a s ignificant effect on the approach scalability. Finally, by using threshold voltage for ID creation, we are able to quantify the probability of coincidence between legitimate and pirated ICs, thus for the first time quantitatively and accurately demonstrating the effectiveness of a hardware metering approach.

show abstract

Section: Related Workmentioning

confidence: 99%

Robust passive hardware metering

Wei¹,

Nahapetian²,

Potkonjak³

2011

2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

View full text Add to dashboard Cite

show abstract

“…A main ramification of NBTI is a significant speed degradation of the pertinent gates ( [1], [6] ). Employment of device aging has been proposed for software metering ( [7]), hardware-based cryptography ( [8]), and prevention of reverse engineering ( [2]). …”

Section: Related Workmentioning

confidence: 99%

“…Passive metering techniques have low cost overhead but they do not provide enforcement mechanisms ( [21]). Dabiri et al proposed the addition of a high area and energy specialty circuitry for the remote chip enabling and disabling and the software usage metering ( [7]). …”

Section: Related Workmentioning

confidence: 99%

A Benign Hardware Trojan on FPGA-based embedded systems

Zheng

Chen

Potkonjak

2012

22nd International Conference on Field Programmable Logic and Applications (FPL)

View full text Add to dashboard Cite

In this paper we present the use of Benign Hardware Trojans (BHT) as a security measure for an embedded system with a software component and a hardware execution environment. Based on delay logic, process variation, and selective transistor aging, the BHT can be incorporated into an embedded system for the software and the hardware components to authenticate each other before functional execution. We will demonstrate an implementation of such a BHT within an embedded system on a Xilinx Spartan-6 FPGA platform. Using the same platform we will also show that the BHT security measurement has a low to modest amount of performance overhead basing on the test results from a variety of synthetic and real world benchmarks.

show abstract

“…Our techniques make no assumptions about the correlation of manufacturing variability across gates, and thus our approach is more robust and realistic. [17] uses convex programming to determine gate level characteristics. Its applicability is limited to butterfly networks, where a path exists from each input to each output.…”

Section: Related Workmentioning

confidence: 99%

SVD-Based Ghost Circuitry Detection

Nelson¹,

Nahapetian²,

Koushanfar

et al. 2009

Information Hiding

View full text Add to dashboard Cite

Abstract. Ghost circuitry (GC) insertion is the malicious addition of hardware in the specification and/or implementation of an IC by an attacker intending to change circuit functionality. There are numerous GC insertion sources, including untrusted foundries, synthesis tools and libraries, testing and verification tools, and configuration scripts. Moreover, GC attacks can greatly compromise the security and privacy of hardware users, either directly or through interaction with pertinent systems, application software, or with data. GC detection is a particularly difficult task in modern and pending deep submicron technologies due to intrinsic manufacturing variability. Here, we provide algebraic and statistical approaches for the detection of ghost circuitry. A singular value decomposition (SVD)-based technique for gate characteristic recovery is applied to solve a system of equations created using fast and non-destructive measurements of leakage power and/or delay. This is then combined with statistical constraint manipulation techniques to detect embedded ghost circuitry. The effectiveness of the approach is demonstrated on the ISCAS 85 benchmarks.

show abstract

Hardware aging-based software metering

Cited by 17 publications

References 6 publications

Robust passive hardware metering

Robust passive hardware metering

A Benign Hardware Trojan on FPGA-based embedded systems

SVD-Based Ghost Circuitry Detection

Contact Info

Product

Resources

About