Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm

Abstract

Packet classification is a ubiquitous and key building block for many critical network devices. However, it remains as one of the main bottlenecks faced when designing fast network devices. In this paper, we propose a novel Group Based Search packet classification Algorithm (GBSA) that is scalable, fast, and efficient. GBSA consumes an average of 0.4 Megabytes of memory for a 10 k rule set. The worst-case classification time per packet is 2 microseconds, and the preprocessing speed is 3 M rules/second based on a Xeon processor operating at 3.4 GHz. When compared with other state-of-the-art classification techniques, the results showed that GBSA outperforms the competition with respect to speed, memory usage, and processing time. Moreover, GBSA is amenable to implementation in hardware. Three different hardware implementations are also presented in this paper including an Application Specific Instruction Set Processor (ASIP) implementation, and two pure Register-Transfer Level (RTL) implementations based on Impulse-C and Handel-C flows, respectively. Speedups achieved with these hardware accelerators ranged from 9x to 18x compared with a pure software implementation running on a Xeon processor.

An Impulse-C Hardware Accelerator for Packet Classification Based on Fine/Coarse Grain Optimization

“…Several novel packet classification algorithms targeting reconfigurable computing platforms (mapped on FPGAs) have been published in recent years [17][18][19][20][21]. In [17] several accelerators based on hardware/software codesign and Handel-C were proposed.…”

“…The hardware accelerators proposed achieved different speedups over a traditional generalpurpose processor. In [21], a novel algorithm (GBSA) is proposed. The GBSA was evaluated and compared to several state-of-the-art techniques including RFC, HiCut, Tuple, and PCIU.…”

“…Results obtained indicate that the GBSA outperforms these algorithms in terms of speed, memory usage, and preprocessing time. The GBSA algorithm introduced in [21] was mapped into hardware using different ESL flows (Impulse-C and Handel-C). The resulting hardware accelerator based on the above mentioned ESL techniques achieved on average 9x speedup.…”

“…For each table entry in Step 2, identify any duplicate entries. For example, rules 1 and 3 are represented by the same start and end values: (21,21). Therefore, the table entry associated with rule 3 can be considered redundant.…”

“…Comparing the PCIU and GBSA Algorithms. Based on results obtained in [21] the GBSA algorithm achieves better performance over the proposed PCIU algorithm in terms of preprocessing and classification time when implemented High Medium on a general-purpose processor (Xeon 3.4 GHz with 2 G RAM). However, as the two implementations are mapped into hardware (RTL translation) using the Impulse-C tools the performance achieved by the PCIU algorithm surpasses that obtained by the GBSA algorithm.…”