2017
DOI: 10.1007/s11265-017-1282-2
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Hardware Accelerators for Iris Localization

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Cited by 10 publications
(11 citation statements)
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“…Our FPGA based architecture for a real-time implementation of the 1D Hough transform multi-circles detection is focused on the acceleration of the construction of histograms V x and V y, [1 -7] and [8][9][10][11][12][13][14] respectively to the algorithm 1. Our solution significantly reduces the use of memory and the latency execution.…”
Section: Proposed Methodsmentioning
confidence: 99%
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“…Our FPGA based architecture for a real-time implementation of the 1D Hough transform multi-circles detection is focused on the acceleration of the construction of histograms V x and V y, [1 -7] and [8][9][10][11][12][13][14] respectively to the algorithm 1. Our solution significantly reduces the use of memory and the latency execution.…”
Section: Proposed Methodsmentioning
confidence: 99%
“…Our solution significantly reduces the use of memory and the latency execution. First, we propose an equivalent algorithm, algorithm 2, which gives the same results, that is to say the same x-coordinate and y-coordinate histograms as in steps [1 -7] and [8][9][10][11][12][13][14] of the algorithm 1.…”
Section: Proposed Methodsmentioning
confidence: 99%
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