Hardware acceleration in the IBM PowerEN processor

Krishna, Anil; Heil, Timothy; Lindberg, Nicholas; Toussi, Farnaz; VanderWiel, Steven

doi:10.1145/2370816.2370872

Cited by 31 publications

(13 citation statements)

References 13 publications

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“…Given the importance of low-latency, high-bandwidth memory accesses for accelerators' performance, private memory blocks take a substantial portion of accelerators' area. For instance, a survey of eleven publicly available accelerators reveals that "an average of 69% of accelerator area is consumed by memory" [24], and recent high-performance accelerators show significant private memory investments as well [5,19].…”

Section: Recent Work On Non-programmable Accelerators Hinges On Two Mmentioning

confidence: 99%

“…The need for greater heterogeneity as a response to the end of Dennard scaling [12] was made evident by Venkatesh et al [37], who proposed the combination of traditional processor cores and energy-efficient specialized cores in the same die. Heterogeneity, by integrating high-performance accelerators on-chip, has been growing in interest, with work coming from academia [5,31,38] and industry [19,20]. In this context, the importance of PLMs is confirmed by the amount of area dedicated to accelerators' memory [24]; this key role of PLMs has sparked recent efforts to automate and optimize the design of heavily banked memory subsystems for accelerators [30].…”

Section: Additional Related Workmentioning

confidence: 99%

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Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration

Cota

Mantovani

Carloni

2016

Proceedings of the 2016 International Conference on Supercomputing

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We present Roca, a technique to reduce the opportunity cost of integrating non-programmable, high-throughput accelerators in general-purpose architectures. Roca exploits the insight that non-programmable accelerators are mostly made of private local memories (PLMs), which are key to the accelerators' performance and energy efficiency. Roca transparently exposes PLMs of otherwise unused accelerators to the cache substrate, thereby allowing the system to extract utility from accelerators even when they cannot directly speed up the system's workload. Roca adds low complexity to existing accelerator designs, requires minimal modifications to the cache substrate, and incurs a modest area overhead that is almost entirely due to additional tag storage. We quantify the utility of Roca by comparing the returns of investing area in either regular last-level cache banks or Roca-enabled accelerators. Through simulation of nonaccelerated multiprogrammed workloads on a 16-core system, we extend a 2MB S-NUCA baseline system to show that a 6MB Roca-enabled last-level cache built upon typical accelerators (i.e. whose area is 66% memory) can, on average, realize 70% of the performance and 68% of the energy efficiency benefits of a same-area 8MB S-NUCA configuration, in addition to the potential orders-of-magnitude efficiency and performance improvements that the added accelerators provide to workloads suitable for acceleration. CCS Concepts •Hardware → Hardware accelerators; Economics of chip design and manufacturing; On-chip resource management; •Computer systems organization → Heterogeneous (hybrid) systems;

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Section: Recent Work On Non-programmable Accelerators Hinges On Two Mmentioning

confidence: 99%

Section: Additional Related Workmentioning

confidence: 99%

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration

Cota

Mantovani

Carloni

2016

Proceedings of the 2016 International Conference on Supercomputing

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“…There have been many proposed hardware approaches for accelerating patternmatching problems [7,11,12,15,22]. Recently, there has been been a renewed focus on accelerating patternrecognition problems using devices such as IBM's Pow-erEN Processor [13], the Titan IC RXP Regular eXpression Processor [20], and the Automata Processor (AP) [10]. The PowerEN processor contains special accelerators alongside traditional cores to allow for improved regular expression performance.…”

Section: Background and Related Workmentioning

confidence: 99%

RAPID Programming of Pattern-Recognition Processors

Angstadt

Weimer

Skadron

2016

SIGARCH Comput. Archit. News

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We present RAPID, a high-level programming language and combined imperative and declarative model for programming pattern-recognition processors, such as Micron's Automata Processor (AP). The AP is a novel, non-Von Neumann architecture for direct execution of non-deterministic finite automata (NFAs), and has been demonstrated to provide substantial speedup for a variety of data-processing applications. RAPID is clear, maintainable, concise, and efficient both at compile and run time. Language features, such as code abstraction and parallel control structures, map well to pattern-matching problems, providing clarity and maintainability. For generation of efficient runtime code, we present algorithms to convert RAPID programs into finite automata. Further, we introduce a tessellation technique for configuring the AP, which significantly reduces compile time, increases programmer productivity, and improves maintainability. We evaluate five RAPID programs against custom, baseline implementations previously demonstrated to be significantly accelerated by the AP. We find that RAPID programs are much shorter in length, are expressible at a higher level of abstraction than their handcrafted counterparts, and yield generated code that is often more compact. In addition, our tessellation technique for configuring the AP has comparable device utilization to, and results in compilation that is up to four orders of magnitude faster than, current solutions.

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“…The IBM PowerEN processor [23] contains accelerators for tasks (cryptography, compression, XML parsing) of importance for web services. Altera [1] provides custom FPGA circuitry for OpenCL.…”

Section: Related Workmentioning

confidence: 99%

Disengaged scheduling for fair, protected access to fast computational accelerators

Menychtas

Shen

Scott

2014

Proceedings of the 19th International Conference on Architectural Support for Programming Languages and Operating Systems

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Today's operating systems treat GPUs and other computational accelerators as if they were simple devices, with bounded and predictable response times. With accelerators assuming an increasing share of the workload on modern machines, this strategy is already problematic, and likely to become untenable soon. If the operating system is to enforce fair sharing of the machine, it must assume responsibility for accelerator scheduling and resource management.Fair, safe scheduling is a particular challenge on fast accelerators, which allow applications to avoid kernel-crossing overhead by interacting directly with the device. We propose a disengaged scheduling strategy in which the kernel intercedes between applications and the accelerator on an infrequent basis, to monitor their use of accelerator cycles and to determine which applications should be granted access over the next time interval.Our strategy assumes a well defined, narrow interface exported by the accelerator. We build upon such an interface, systematically inferred for the latest Nvidia GPUs. We construct several example schedulers, including Disengaged Timeslice with overuse control that guarantees fairness and Disengaged Fair Queueing that is effective in limiting resource idleness, but probabilistic. Both schedulers ensure fair sharing of the GPU, even among uncooperative or adversarial applications; Disengaged Fair Queueing incurs a 4% overhead on average (max 18%) compared to direct device access across our evaluation scenarios.

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Hardware acceleration in the IBM PowerEN processor

Cited by 31 publications

References 13 publications

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration

Exploiting Private Local Memories to Reduce the Opportunity Cost of Accelerator Integration

RAPID Programming of Pattern-Recognition Processors

Disengaged scheduling for fair, protected access to fast computational accelerators

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