Hardware acceleration for programs in SSA form

Optimal Shuffle Code with Permutation Instructions

“…In this section we prove the optimality of the greedy algorithm proposed by Mohr et al [8] for outdegree-1 RTGs. Before we formulate the algorithm, let us look at the effect of applying a transposition τ = (u v) to contiguous vertices of a k-cycle K =…”

“…The shuffle code generation problem asks for a shortest shuffle code that implements a given RTG. The amount of shuffle code directly depends on the quality of copy coalescing, a subtask of register allocation [8]. As copy coalescing is NP-complete [2], reducing the amount of shuffle code is expensive in terms of compilation time, and thus cannot be afforded in all contexts, e.g., just-in-time compilation.…”

“…Therefore, it has been suggested to allow more complicated operations than simply copying and swapping to enable more efficient shuffle code. Mohr et al [8] propose to allow performing permutations on the contents of small sets of up to five registers. The processor they develop offers three instructions to implement shuffle code: copy: copies the content of one register to another one permi5: cyclically shifts the contents of up to five registers permi23: swaps the contents of two registers and performs a cyclic shift of the contents of up to three registers; the two sets of registers must be disjoint.…”

“…During register allocation, the compiler may introduce shuffle code, consisting of copy and swap operations, that transfers data between the registers. Three common sources of shuffle code are conflicting register mappings at joins in the control flow of the program, e.g, due to if-statements or loops; the calling convention for procedures, which often dictates that input arguments or results must be placed in certain registers; and machine instructions that only allow a subset of registers to occur as operands.Recently, Mohr et al [8] proposed to speed up shuffle code with special hardware instructions that arbitrarily permute the contents of up to five registers and gave a heuristic for computing such shuffle codes. In this paper, we give an efficient algorithm for generating optimal shuffle code in the setting of Mohr et al An interesting special case occurs when no register has to be transferred to more than one destination, i.e., it suffices to permute the contents of the registers.…”

“…Recently, Mohr et al [8] proposed to speed up shuffle code with special hardware instructions that arbitrarily permute the contents of up to five registers and gave a heuristic for computing such shuffle codes. In this paper, we give an efficient algorithm for generating optimal shuffle code in the setting of Mohr et al An interesting special case occurs when no register has to be transferred to more than one destination, i.e., it suffices to permute the contents of the registers.…”