Hardware Acceleration for Neuromorphic Vision Algorithms

Maashri, Ahmed Al; Cotter, Matthew; Chandramoorthy, Nandhini; DeBole, Michael; Yu, Chi-Li; Narayanan, Vijaykrishnan; Chakrabarti, Chaitali

doi:10.1007/s11265-012-0699-x

Cited by 6 publications

(12 citation statements)

References 14 publications

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“…Section III introduces the system architecture for the proposed FPGA-based AES coprocessor. Section IV describes the implementation details of the reconfigurable AES engine, followed by an overview of the Vortex data router [15,16,17,18] in Section V. Section VI describes the resource performance controller of our design. Workflow simulations are presented in Section VII, followed by performance validation and tradeoff analysis in Section VIII.…”

Section: Us Government Work Not Protected By Us Copyrightmentioning

confidence: 99%

“…2. Our cryptographic architecture is comprised of several components: an AES engine, a multi-level resources optimization controller and Vortex data router [15]. Data encryption and decryption are handled by the AES engine which is capable of supporting multiple levels of security.…”

Section: System Arhitecture For the Aes Coprocessormentioning

confidence: 99%

“…The MixColumns module allows for the same modes of operation as AddRoundKey and SubBytes: BYTE, COLUMN, and STATE. This MixColumns implementation requires an additional cycle to generate the appropriate multiples of each byte in the column; this additional cycle of latency is hidden in both COLUMN and STATE modes by overlapping these multiple-generations with calculations from previous operations V. VORTEX DATA ROUTER Vortex [15] is a reconfigurable and highly programmable Network-on-Chip (NoC) platform. It is based on the NoC paradigm, its main distinguishing attributes are the optimized network interfaces that ease the mapping of dataflow graphs onto System-on-Chip (SoCs).…”

Section: E Mixcolumns Modulementioning

confidence: 99%

“…The popularity of these devices introduces a new class of portable applications that are power aware and dynamically adapted to task needs in resource constrained hostile environment where secure collection, processing and transmission of time-critical sensitive data is a necessity. This class of portable applications requires the endowment of a light-weight advanced cryptographic system such as a Trusted Platform Module [10], [11], [12], and [13] implemented on-board of the mobile device to assure data integrity, point-to-point communication, authentication [14], and [15], confidentiality, and nonrepudiation. Furthermore, run-time adaption to task dynamics in resource-constrained environment demands the inclusion of critical in situ reasoning and collaborative decision-making capabilities to these mobile devices.…”

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Dynamically reconfigurable AES cryptographic core for small, power limited mobile sensors

Rasheed

Cotter

Smith

et al. 2016

2016 IEEE 35th International Performance Computing and Communications Conference (IPCCC)

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In this paper, we propose a dynamically run-time reconfigurable power aware cryptographic processor for secure autonomous encryption. The design proposes the implementation of a dynamically reconfigurable AES cryptography process on an FPGA. The proposed design encompasses a microarchitecture which is variously power, latency, and throughput optimized via hardware acceleration and partial reconfiguration by a multi-level autonomic controller and a data router to enable tradeoffs under changing operational requirements within resource constraints. The multi-level controller decides on the appropriate configuration based on varying operational workloads to characterize the effect that time-varying task parameters have on the hardware architecture, to enable a run-time tradeoff of performance and resources usage (Key length, computational efficiency, latency and throughput).

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Section: Us Government Work Not Protected By Us Copyrightmentioning

confidence: 99%

Section: System Arhitecture For the Aes Coprocessormentioning

confidence: 99%

Section: E Mixcolumns Modulementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Dynamically reconfigurable AES cryptographic core for small, power limited mobile sensors

Rasheed

Cotter

Smith

et al. 2016

2016 IEEE 35th International Performance Computing and Communications Conference (IPCCC)

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“…For example, Farabet et al [11] introduce NeuFlow, a FPGAbased dataflow processor designed explicitly to maximize performance with convolutional neural network algorithms. The authors of [2] also propose a multi-FPGA system to efficiently implement neuromorphic algorithms based on the HMAX model. Targeting FPGAs requires essentially designing custom HW to deploy on expensive chips; by contrast, we focus on mobile chips that are ∼10x less expensive and programmable in SW by a much larger community.…”

Section: Related Workmentioning

confidence: 99%

Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform

Conti

Pullini

Benini

2014

2014 IEEE Conference on Computer Vision and Pattern Recognition Workshops

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Brain-inspired computer vision (BICV) has evolved rapidly in recent years and it is now competitive with traditional CV approaches. However, most of BICV algorithms have been developed on high power-and-performance platforms (e.g. workstations) or special purpose hardware. We propose two different algorithms for counting people in a classroom, both based on Convolutional Neural Networks (CNNs), a state-of-art deep learning model that is inspired on the structure of the human visual cortex. Furthermore, we provide a standalone parallel C library that implements CNNs and use it to deploy our algorithms on the embedded mobile ARM big.LITTLE-based Odroid-XU platform. Our performance and power measurements show that neuromorphic vision is feasible on off-the-shelf embedded mobile platforms, and we show that it can reach very good energy efficiency for non-time-critical tasks such as people counting.

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Optimal Tiling Strategy for Memory Bandwidth Reduction for CNNs

Cecconi

Smets

Benini

et al. 2017

Advanced Concepts for Intelligent Vision Systems

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Convolutional Neural Networks (CNNs), are nowadays present in many different embedded solutions. One of the biggest problems related to their execution is the memory bottleneck. In this work we propose an optimal double buffering tiling strategy, to reduce the memory bandwidth in the execution of deep CNN architecture, testing our model on one of the two cores of a Zynq®-7020 embedded platform. An optimal tiling strategy is found for each layer of the network, optimizing for lowest external memory On-Chip memory bandwidth. Performance test results show an improvement in the total execution time of 50% (cache disabled / 34% cache enabled), compared to a non double buffered implementation. Moreover, a 5x lower external memory On-Chip memory double buffering memory bandwidth is achieved, with respect to naive tiling settings. Furthermore it is shown that tiling settings for highest OCM usage do not generally lead to the lowest bandwidth scenario.

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Hardware Acceleration for Neuromorphic Vision Algorithms

Cited by 6 publications

References 14 publications

Dynamically reconfigurable AES cryptographic core for small, power limited mobile sensors

Dynamically reconfigurable AES cryptographic core for small, power limited mobile sensors

Brain-Inspired Classroom Occupancy Monitoring on a Low-Power Mobile Platform

Optimal Tiling Strategy for Memory Bandwidth Reduction for CNNs

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