Audio processing and especially MP3 decoding is usually implemented by software due to the complexity of its hardware alternative. This work proposes a hardware solution to one of the most critical parts of an MP3 decoder, the polyphase filter bank. The aim is to improve its operation rate while saving power. The proposal takes advantage of the DSP-oriented architecture of modern FPGAs. Sequential operations in software can be parallelised in hardware and time critical functions can be accelerated. The Altera's Stratix EP1S10F780C6ES FPGA was used as hardware support. DSP Builder design tools was used together with Matlab and Quartus II in order to simplify the design and simulation tasks. As a result, a synthesis polyphase filter bank, working in real time, was designed and tested.