Hardening measures for bipolar transistors against microwave-induced damage

Abstract

In the present paper we study the influences of the bias voltage and the external components on the damage progress of a bipolar transistor induced by high-power microwaves. The mechanism is presented by analyzing the variation in the internal distribution of the temperature in the device. The findings show that the device becomes less vulnerable to damage with an increase in bias voltage. Both the series diode at the base and the relatively low series resistance at the emitter, R e , can obviously prolong the burnout time of the device. However, R e will aid damage to the device when the value is sufficiently high due to the fact that the highest hot spot shifts from the base-emitter junction to the base region. Moreover, the series resistance at the base R b will weaken the capability of the device to withstand microwave damage.

Modeling and understanding of the frequency dependent HPM upset susceptibility of the CMOS inverter

“…It is obvious that the overall trends of both our proposed model and the experimental data are in complete accord and behave linear in the double log-log coordinate, though they are in different units. There is a slight discrepancy at relatively low frequency (f 1 GHz) between our model (15) and the experimental data, which is due to the assumption that the coefficient α indicating the frequency dependence is a constant, while in fact, the frequency dependence will be weakened at low frequency. Hence the accuracy of our model can be improved by utilizing a variable α extracted from more experimental data.…”

“…Besides, the total amount of injected charges is verified to be proportional to f −0.525 and the excess carrier density distribution also demonstrates frequency dependence; This dependence is attributable to the fact that the AC field within CMOS inverter varies too rapidly for the carriers to follow, which is concluded to be the physical essential of the frequency dependent HPM upset susceptibility. The analytical models (15) and (16) can be used to quickly estimate the HPM upset susceptibility of a CMOS inverter taking the influence of ICs fabrication, pulse properties and operating environment into account simultaneously. In the end, the influence of the layout parameter L B on the HPM susceptibility level is acquired, demonstrating that CMOS inverter with minor L B is more susceptible to HPM.…”

“…Generally the HPM radiation energy couples into interior electronics of a system through either the front-door or back-door path [14]. In this investigation the HPM is assumed as a sinusoidal plane wave without attenuation [15], and is injected into "NS" contact to simulate the process that the HPM energy couples into a single gate inverter through the back-door path.…”

“…From (15), the influence of f on V p is acquired and depicted in Figure 9. Afterwards, HPMs with a pulse-width of 10 ns, PRF of 0, and frequency varying from 500 MHz to 8 GHz are successively exerted on CMOS inverter by the simulation method.…”

Upset and damage mechanisms of the three-dimensional silicon device induced by high power microwave interference

“…Yu et al analytically discussed and deduced the effects of HPM frequency, HPM pulse-width and temperature on CMOS inverter by analyzing fundamental physical parame-ters [18,19,20]. For other types of circuits and devices, Ma et al and Chai et al explained the failure mechanism induced by HPM of bipolar transistor and proposed several protective measures [21,22,23,24,25]. However, some theoretical analysis of CMOS inverter and their associated circuits under the influence of HPM interference still need to be further solved, such as bit error and damage.…”