Haptic rendering of deformable objects using a multiple FPGA parallel computing architecture

A Multiple-FPGA parallel computing architecture for real-time simulation of soft-object deformation

“…Given the special matrix structure described in PL1, this format can reduce the memory needed for storing elements of d for a particular subpartition to less than one third of the required memory for storing nonzero elements of the matrix in that subpartition. Therefore unlike in our earlier architecture in Mahdavikhah et al [2010], the required memory for storing d vector is not dependent on L or N.…”

“…This quad-FPGA system has enabled real-time simulation of haptic interaction with a 3D FE model of 6000 nodes (∼21000 elements) at update rate of 400Hz. Using the same FPGAs, the quad-FPGA architecture in this article results in an 8.4 fold increase in the number of arithmetic operations per second compared to the single-FPGA design in Mafi et al [2009], and a 2.6-fold increase compared to the earlier quad-FPGA design in Mahdavikhah et al [2010].…”

“…Operating at the clock frequency of 100 MHz leads to a SpMxV kernel that can operate at a rate of 604 Giga Operations Per Second (GOPS). In Table VIII, the performance of the proposed architecture has been compared with that of three different microprocessors used in the experiments conducted by Goumas et al [2008], the GPU platform in Bell and Garland [2008], the single-FPGA architecture in Mafi et al [2009] and previous quad-FPGA desgin in [Mahdavikhah et al 2010]. The last column compares the average results in the fourth column to the speed of computation in the architecture proposed in this article.…”

“…The system consists of a custom 3DOF haptic interface, a Quanser QPA linear current amplifier, a Quanser Q4 hardware-in-the-loop data acquisition board, a Gidel PROCStar III development board with four Altera Stratix III EP3S110E FPGA Table VIII. Comparative performance of SpMxV kernel on general-purpose CPUs [Goumas et al 2008], GeFORCE GPU [Bell and Garland 2008], a single FPGA-based design [Mafi et al 2009] and the former quad-FPGA architecture in [Mahdavikhah et al 2010] with the proposed quad-FPGA hardware accelerator.…”

“…In Mahdavikhah et al [2010], we introduced an early version of the multi-FPGA architecture. That design can process larger FE meshes compared with the one in Mafi et al [2009] but its resource requirements per FPGA grow linearly by the number of the FPGAs.…”