Handling complexities in modern large-scale mixed-size placement

Abstract

In this paper, we propose an effective algorithm flow to handle largescale mixed-size placement. The basic idea is to use floorplanning to guide the placement of objects at the global level. The flow consists of four steps: 1) The objects in the original netlist are clustered into blocks; 2) Floorplanning is performed on the blocks; 3) The blocks are shifted within the chip region to further optimize the wirelength; 4) With big macro locations fixed, incremental placement is applied to place the remaining objects. There are several advantages of handling placement at the global level with a floorplanning technique. First, the problem size can be significantly reduced. Second, exact HPWL can be minimized. Third, precise object distribution can be achieved so that legalization only needs to handle minor overlaps among small objects in a block. Fourth, rotation and various placement constraints on macros can be handled. To demonstrate the effectiveness of this new flow, we implement a high-quality floorplanguided placer called FLOP. We also construct the Modern MixedSize (MMS) placement benchmarks which can effectively represent the complexities of modern mixed-size designs and the challenges faced by modern mixed-size placers. Compared with state-of-the-art mixed-size placers and leading macro placers, experimental results show that FLOP achieves the best wirelength, and easily obtains legal solutions on all circuits.

ePlace-MS: Electrostatics-Based Placement for Mixed-Size Circuits

“…• We integrate all the innovations into ePlace-MS, an electrostatics based prototype for mixed-size placement, with promising experimental results obtained on the modern mixed-size (MMS) [47] circuits. Specifically, ePlace-MS outperforms the leading placer NTUplace3 [13] with 8.22% shorter wirelength and the same runtime on average of all the sixteen MMS benchmarks [47].…”

“…Placement quality is usually evaluated by the total half-perimeter wirelength (HPWL), which correlates with timing [29], [48], routability [10], [41], and power [26], subject to the constraint of zero overlap among circuit components. Such problem formulation is broadly used among research developments [3], [5], [15], [17], [18], [45], [46] and well honored by public placement benchmarks [33], [34], [47].…”

“…Capo [39] repeatedly invokes a fixed-outline floorplanner over the top-down placement framework, providing guidance to macro shifting. FLOP [47] groups cells into soft blocks to produce initial floorplan solution. Incremental global [46] and detailed placement further spread and legalize the standard cells within local scale.…”

“…NTUplace3 [13] incorporates rotational and flipping components into the gradient function, which enables simultaneous optimization on the location of all the movable objects as well as the orientation of macros. As mentioned in [47], macro and standard cell co-placement challenges the capability of modern analytic placement approaches. Despite largest search space, nevertheless, the sub-stantial topological and physical differences between macros and standard cells might introduce gradient imbalance and cause the solution hard to converge.…”

“…As a generalized algorithm, ePlace-MS handles standard cells and macros in exactly the same way (c.f. macro shifting when declustering [13], soft block formation by standard cells [46], [47], special macro density smoothing [15], [18], macro shredding [17], etc.) to ensure high and stable performance over various integrated circuits with potentially quite different structures of the design.…”