“…Placement quality is usually evaluated by the total half-perimeter wirelength (HPWL), which correlates with timing [29], [48], routability [10], [41], and power [26], subject to the constraint of zero overlap among circuit components. Such problem formulation is broadly used among research developments [3], [5], [15], [17], [18], [45], [46] and well honored by public placement benchmarks [33], [34], [47].…”