Handling behavioral components in multi-level concurrent fault simulation

Abstract

System level modeling is becoming a necessity in all areas of engineering design. As systems grow in complexity, designers may increasingly rely on commercial off-the-shelf (COTS) components. Frequently, these components are described at a high level of abstraction (behaviorally) that complicates fault testing. This paper discusses the trade-offs of using behavioral components in a design, specifically as it relates to fault simulation. We investigate important issues such as timing, and examine the need to internally fault behavioral models. We then present our multi-level concurrent fault simulator (MCS) that can accept any combination of gate level and behavioral models using a single kernel. Our kernel propagates faults through behavioral components deterministically. Finally, we present simulation results of multi-level models to demonstrate our simulator's capabilities and performance.

Efficient Simulation of Structural Faults for the Reliability Evaluation at System-Level

“…• Multi-level simulation of switch-level and gate-level representations [9] • Serial simulation of structural faults in mixed-level gatelevel/RTL models with event-based simulators [10,11] • Mixed-level fault-simulation of gate-level and RTL using concurrent simulation [12,13] • Simulation of structural faults in mixed-level gatelevel/architectural-level simulations with symbolic simulation in the architecture-level model [14,15] • Serial fault injections performed at RT-level with error propagation at system-level [5] • Injection of structural faults into mixed gate-level/highlevel SystemC models [16] • Mutator-based injection of faults into RTL and transaction-level models [17] The work presented here is the first approach that efficiently implements concurrent multi-level fault simulation across gate-and transaction-level in an integrated simulation environment. Our work is based on a structural fault model with an efficient concurrent fault simulator at gate-level.…”