H.264/AVC UHD decoder implementation on multi-cluster platform using hybrid parallelization method

Lee, Sangjo; Song, Joonho; Kim, Min‐Soo; Kim, Dohyung; Lee, Shihwa

doi:10.1109/icip.2011.6116529

Cited by 6 publications

(2 citation statements)

References 5 publications

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“…An in-depth analysis of the CGRA instruction was conducted using a high performance H.264 decoder [9] compiled by SRP-SDK,which is a state-of-the-art CGRA compiler with an advanced modulo scheduling algorithm [10]. The first interesting finding discovered through our observation is that many frequently executed code on a specific FU are also frequently executed on other FUs in a CGRA.…”

Section: B Instruction Analysis and Lessonsmentioning

confidence: 95%

Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures

Chung

Kim

Cho

et al. 2013

2013 International Conference on Field-Programmable Technology (FPT)

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Coarse Grained Reconfigurable Architecture (CGRA) achieves high performance by exploiting instructionlevel parallelism with software pipeline. Large instruction memory is, however, a critical problem of CGRA, which requires large silicon area and power consumption. Code compression is a promising technique to reduce the memory area, bandwidth requirements, and power consumption. We present an adaptive code compression scheme for CGRA instructions based on dictionary-based compression, where compression mode and dictionary contents are adaptively selected for each execution kernel and compression group. In addition, it is able to design hardware decompressor efficiently with two-cycle latency and negligible silicon overhead. The proposed method achieved an average compression ratio 0.52 in a CGRA of 16-functional unit array with the experiments of well-optimized applications.

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Section: B Instruction Analysis and Lessonsmentioning

confidence: 95%

Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures

Chung

Kim

Cho

et al. 2013

2013 International Conference on Field-Programmable Technology (FPT)

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“…The Samsung reconfigurable processor (SRP) is a derivative of the ADRES CGRA architecture [69], [70].…”

Section: ) Coarse-grainedmentioning

confidence: 99%

Reconfigurable Computing Architectures

2015

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This paper provides an overview of the broad body-of-knowledge developed in the field of reconfigurable computing.ABSTRACT | Reconfigurable architectures can bring unique capabilities to computational tasks. They offer the performance and energy efficiency of hardware with the flexibility of software. In some domains, they are the only way to achieve the required, real-time performance without fabricating custom integrated circuits. Their functionality can be upgraded and repaired during their operational lifecycle and specialized to the particular instance of a task. We survey the field of reconfigurable computing, providing a guide to the body-ofknowledge accumulated in architecture, compute models, tools, run-time reconfiguration, and applications.

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Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders

Ahn

Yoo

et al. 2017

J Real-Time Image Proc

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H.264/AVC UHD decoder implementation on multi-cluster platform using hybrid parallelization method

Cited by 6 publications

References 5 publications

Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures

Adaptive compression for instruction code of Coarse Grained Reconfigurable Architectures

Reconfigurable Computing Architectures

Software pipelining with CGA and proposed intrinsics on a reconfigurable processor for HEVC decoders

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