H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture

Nousias, I.; Khawam, S.; Milward, M.; Arslan, Tughrul

doi:10.1109/ahs.2007.58

Cited by 7 publications

(2 citation statements)

References 8 publications

(7 reference statements)

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“…Major et al [8] propose a dynamically reconfigurable instruction cell architecture processor [9] in which the instruction control is similar to the control in Very Long Instruction Word (VLIW) architectures. The designed architecture consists of a coarse grained reconfigurable fabric of interconnected instruction cells.…”

Section: Related Workmentioning

confidence: 99%

Programmable in-loop deblock filter processor for video decoders

Janhunen

Jääskeläinen

Hannuksela

et al. 2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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The short time to market cycle and the target to reduce design and verification costs are driving forces to design programmable implementations of the video processing algorithms. We present two processor architectures the first one representing an application-specific instruction set processor (ASIP) design, whereas the second architecture represents a domain-specific instruction-set processor (DSIP) architecture with more general purpose instruction-set. In this work, we present results for H264 and VP8 in-loop deblocking algorithms. The processors are based on the transport triggered architecture which provides scalable instruction-level parallelism and, thanks to its simple structure, lend itself to cost effective designs. Both of the designs are programmed with C language with a minimal additional parallelism markup. The designs fulfill realtime requirements for filtering macroblocks in high-definition video. The first architecture, based on special function units, filters a high-definition stream (1920 × 1080) at 75 fps, whereas the second architecture, which provides a better programmability, filters the stream at 53 fps. The processors run on 200 MHz clock frequency and the areas vary from 146k to 373k gate equivalents depending on the processor architecture.

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Section: Related Workmentioning

confidence: 99%

Programmable in-loop deblock filter processor for video decoders

Janhunen

Jääskeläinen

Hannuksela

et al. 2014

2014 IEEE Workshop on Signal Processing Systems (SiPS)

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“…The filtering algorithm is very complex. This is due to the highly adaptive nature of the algorithm of the deblocking filter, as well as to the huge quantity of pixel data to be read from memory and processed [7][8] [9].…”

Section: Complexitymentioning

confidence: 99%

Porting a H264/AVC Adaptive in Loop Deblocking Filter to a TI DM6437EVM DSP

Abdellah

Mokhtar

Serir

2012

Lecture Notes in Computer Science

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Complementary units in the form encoders and decoders are generally involved in video compression standards. Both the encoder and the decoder integrate an adaptive deblocking filter, which is very beneficial in preserving and enhancing the video quality. Deblocking filters are extremely popular in improving the visual quality of decoded frames in the H.264/AVC video coding standard. The prime goal of the current paper is to efficiently implement a H.264/AVC adaptive deblocking filter using the Texas Instruments DM6437EVM DSP processor. The adopted approach requires an initial identification of the portions of the algorithm wherein parallel processing can be exploited. The functions are then rewritten and the instructions rearranged using the features of the targeted hardware architecture. The adaptive deblocking algorithm was optimised and ported to a DM6437EVM DSP platform. A quick comparison shows that the optimised code is a 32 % better, in terms of speed, than the non-optimised code.

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A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities

Brunelli

Garzia

Nurmi

2008

J Real-Time Image Proc

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This paper presents the design and the implementation of a coarse-grain reconfigurable machine used as an accelerator for a programmable RISC core, to speed up the execution of computationally demanding tasks like multimedia applications. We created a VHDL model of the proposed architecture and implemented it on a FPGA board for prototyping purposes; then we mapped on our architecture some DSP and image processing algorithms as a benchmark. In particular, we provided the proposed architecture with subword computation capabilities, which turns out to be extremely effective especially when dealing with image processing algorithms, achieving significant benefits in terms of speed and efficiency in resource usage. To create the configuration bitstream (configware) we created a tool based on a graphical user interface (GUI) which provides a first step towards the automation of the programming flow of our design: the tool is meant to ease the life of the programmer, relieving him from the burden of calculating the configuration bits by hand. Synthesis results indicate that the area occupation and the operating frequency of our design are reasonable also when compared to other similar design. In addition to this, the amount of clock cycles taken by our machine to perform a given algorithm is orders of magnitude smaller than the one required by a corresponding software implementation on a RISC microprocessor.

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H.264/AVC In-Loop De-Blocking Filter Targeting a Dynamically Reconfigurable Instruction Cell Based Architecture

Cited by 7 publications

References 8 publications

Programmable in-loop deblock filter processor for video decoders

Programmable in-loop deblock filter processor for video decoders

Porting a H264/AVC Adaptive in Loop Deblocking Filter to a TI DM6437EVM DSP

A coarse-grain reconfigurable architecture for multimedia applications featuring subword computation capabilities

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