GST-memristor-based online learning neural networks

IEEE Trans. Neural Netw. Learning Syst.

Chua

2020

219

120

The volume, veracity, variability and velocity of data produced from the ever increasing network of sensors connected to Internet pose challenges for power management, scalability and sustainability of cloud computing infrastructure. Increasing the data processing capability of edge computing devices at lower power requirements can reduce several overheads for cloud computing solutions. This paper provides the review of neuromorphic CMOS-memristive architectures that can be integrated into edge computing devices. We discuss why the neuromorphic architectures are useful for edge devices and show the advantages, drawbacks and open problems in the field of neuro-memristive circuits for edge computing.

Section: B Neural Network Learning Architecturesmentioning

confidence: 99%

Section: B Major Issues Open Problems and Future Work Prospectivementioning

confidence: 99%

Neuromemristive Circuits for Edge Computing: A Review

IEEE Trans. Neural Netw. Learning Syst.

Chua

2020

219

120

“…It is easier and simpler to switch the memristor to either R ON and R OF F state. The implementation of the analog weights is also possible using 16-level Ge 2 Sb 2 Te 5 (GST) memristors [51]. However, the memristor technology is not mature like CMOS, and even if the memristor can be precisely programmed and work accurately under the controlled environment in the lab, the behavior of the memristor in the multi-level large-scale simulation still needed to be verified.…”

Section: Backpropagation With Memristive Circuits a Overall Arcmentioning

confidence: 99%

“…1) and modular crossbar (shown in Fig. 6) using Ge 2 Sb 2 T e 5 (GST) memristors with 16 resistive levels [65], [51]. In ANN simulation, MNIST database [66] with 70, 000 images of the size of 28 × 28 was used, where 86% of images was selected for testing and 14% for testing.…”

Section: B System Level Simulationsmentioning

confidence: 99%

Learning in Memristive Neural Network Architectures Using Analog Backpropagation Circuits

Salama

IEEE Trans. Circuits Syst. I

2019

123

The on-chip implementation of learning algorithms would speed-up the training of neural networks in crossbar arrays. The circuit level design and implementation of backpropagation algorithm using gradient descent operation for neural network architectures is an open problem. In this paper, we proposed the analog backpropagation learning circuits for various memristive learning architectures, such as Deep Neural Network (DNN), Binary Neural Network (BNN), Multiple Neural Network (MNN), Hierarchical Temporal Memory (HTM) and Long-Short Term Memory (LSTM). The circuit design and verification is done using TSMC 180nm CMOS process models, and TiO2 based memristor models. The application level validations of the system are done using XOR problem, MNIST character and Yale face image databases.

“…The probabilistic weights corresponding to the training stage are stored in the crossbar as a resistance of the memristor. The weights for each separate class are stored in a separate memristive crossbar consisting of GST memristors [11]. Each column of the crossbar corresponds to a particular training sample; therefore, the number of columns in a crossbar represents the number of training samples for a certain class.…”

Section: Approximate Probabilistic Neural Networkmentioning

confidence: 99%

Approximate Probabilistic Neural Networks with Gated Threshold Logic

2018 IEEE 18th International Conference on Nanotechnology (IEEE-NANO)

2018

Probabilistic Neural Network (PNN) is a feed-forward artificial neural network developed for solving classification problems. This paper proposes a hardware implementation of an approximated PNN (APNN) algorithm in which the conventional exponential function of the PNN is replaced with gated threshold logic. The weights of the PNN are approximated using a memristive crossbar architecture. In particular, the proposed algorithm performs normalization of the training weights, and quantization into 16 levels which significantly reduces the complexity of the circuit.