GSM/GPRS Single-Chip in 130nm CMOS: Challenges on RF for SoC Integration

Seippel, D.; Hammes, M.; Hanke, A.; Kissing, J.

doi:10.1109/rfic.2006.1651120

Cited by 4 publications

(2 citation statements)

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“…Smaller footprint and lower cost is driving integration of embedded radios within a SOC, which have become de facto the market norm. Although began with less demanding systems such as Bluetooth, recently WLAN, GSM [1], and combination products (Combos) have been produced. The rate of introduction of CMOS technology nodes, and significant competitive pressure, drives aggressive product development timelines.…”

Section: Introductionmentioning

confidence: 99%

Challenges in integrating embedded RF within a SOC

Ridgers¹,

Boucey²,

Frambach

et al. 2008

2008 IEEE Radio and Wireless Symposium

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The challenges of integrating an embedded RF function within a system-on-chip (SOC) are outlined. An aggressive market need, combined with stringent technical difficulties, drives the need for an improved design methodology. Architecture innovations allow optimal building of RF within advanced CMOS. Antenna coexistence and substrate co-habitation have also to be addressed especially in multi-mode platforms. Only total deployment of design for excellence (DFx) procedures enables achieving production yield and cost goals. Future technology will not only use 32 and 22nm nodes, but probably also SIP-based RF filters and MEMs.

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Section: Introductionmentioning

confidence: 99%

Challenges in integrating embedded RF within a SOC

Ridgers¹,

Boucey²,

Frambach

et al. 2008

2008 IEEE Radio and Wireless Symposium

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“…Despite the additional PMU integration even better performance results have been achieved for the RF as compared to a baseband-radio without integrated PMU [4].…”

mentioning

confidence: 99%

A GSM Baseband Radio in 0.13μm CMOS with Fully Integrated Power-Management

Hammes

Kranz

Kissing

et al. 2007

2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

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The recent past shows tremendous progress in the area of SoC technology, like fully-integrated GSM/GPRS baseband-radios in standard digital CMOS technology, which represent the key component of a mobile phone. After successfully tackling the challenges of RF integration into a digital baseband chip [1], the next step following the SoC path is the integration of the Power-Management Unit (PMU). To achieve optimum cost, an overall system architecture approach has to be selected that considers the chip-architecture as well as the mobile phone architecture. The integrated PMU not only supplies the functional blocks onchip but also delivers power to the other components connected to the chip, e.g. LED display lighting, memory and SIM-card. To further decrease the bill-of-materials for the phone the required RAM memory is integrated on-chip, with the FLASH memory connected externally. A typical application example is shown in Fig. 14.6.1.The chip presented here is derived from the architecture in [1], but, with fundamental extensions, including an integrated PMU (including loudspeaker driver) and fully-integrated RAM. The design faces three major challenges [2,3]: i) the realization of efficient voltage regulators in a digital CMOS technology, ii) electrical and thermal cross-coupling from the regulator and DC/DCconverters to sensitive RF-and audio-circuits, and iii) thermal stress of the CMOS technology.To achieve the direct-to-battery capability for the regulator and the charger, special circuits are used. In addition other functional blocks, which are typically located in a separate PMU device, have to be integrated, such as a loudspeaker driver with high output power or a DC/DC converter to generate higher voltages than the battery voltage. This higher voltage can be used to supply white or blue LED's.The selection of the power supply concept, from either linear or switched regulator types, is in general a trade-off between current consumption and cost. A linear regulator results in higher current consumption due to its lower efficiency. Switched regulators, on the other hand, result in higher cost, e.g., if external inductors or if special technology is required as in the case of direct-to-battery connection. The present architecture makes use of both types of regulators. Due to the performance requirements of an ultra-low cost phone, the chip current consumption has been reduced and therefore the majority of the regulators were chosen to be of the linear type.One major challenge is the high battery voltage (up to 5.5V) compared to the breakdown voltage of the 0.13µm CMOS technology used. This technology provides dual gate oxide transistors (I/O and analog devices) with a drain-source voltage of up to 3.3V. A further increase of the electrical strength requires special design techniques and was achieved by transistor stacking. Theoretically two stacked devices can withstand 6.6V, which is sufficient for the targeted application. Figure 14.6.2 shows the block diagram of a stacked device directto-battery Low-Drop-Ou...

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