Growth of High-Quality Ge Epitaxial Layers on Si (100)

Abstract

A method of growing high-quality epitaxial Ge layers on a Si(100) substrate is reported. In this method, a 0.8 mm Si 0:1 Ge 0:9 layer was first grown. Due to the large lattice mismatch between this layer and the Si substrate, many dislocations form near the interface and in the lower part of the Si 0:1 Ge 0:9 layer. A 0.8 mm Si 0:05 Ge 0:95 layer and a 1.0 mm top Ge layer were subsequently grown on the Si 0:1 Ge 0:9 layer. The formed interfaces of Si 0:05 Ge 0:95 /Si 0:1 Ge 0:9 and Ge/Si 0:05 Ge 0:95 can bend and terminate the upward-propagated dislocations very effectively. The in situ annealing process was also performed for each individual layer. Experimental results show that the dislocation density in the top Ge layer can be greatly reduced, and the surface is very smooth, while the total thickness of the structure is only 2.6 mm.

The influence of low-temperature Ge seed layer on growth of high-quality Ge epilayer on Si(100) by ultrahigh vacuum chemical vapor deposition

“…Several methods have been exploited to grow high-quality Ge film on Si substrate, such as those using compositionally graded buffer layer [4,5], two thin SiGe buffer layers [6], surfactant-mediated epitaxy [7], selective area growth [8], and low temperature (LT) and high temperature (HT) twostep growth approach combined with thermal annealing [9,10]. However, the graded SiGe buffer layers are required to be about 10 mm thickness with Ge composition ranging from 0 to 1, which is not appropriate for monolithic integration of devices on Si and has poor thermal conduction.…”

“…However, the graded SiGe buffer layers are required to be about 10 mm thickness with Ge composition ranging from 0 to 1, which is not appropriate for monolithic integration of devices on Si and has poor thermal conduction. In order to reduce the buffer layer's thickness, double thin SiGe layers utilizing interface blocking and in situ annealing has been reported [6]. Ge epilayer with a threading dislocation density (TDD) of 3 Â 10 6 cm À2 and root-mean-square (RMS) surface roughness of 3.2 nm was achieved [6].…”

“…In order to reduce the buffer layer's thickness, double thin SiGe layers utilizing interface blocking and in situ annealing has been reported [6]. Ge epilayer with a threading dislocation density (TDD) of 3 Â 10 6 cm À2 and root-mean-square (RMS) surface roughness of 3.2 nm was achieved [6]. The total thickness of the double thin SiGe buffer layers is about 1.6 mm, which is still too thick for practical integration.…”

Ge on Si Photodiodes for Si CMOS Monolithic Optical Receivers

“…Hence it is crucial to reduce the threading dislocation density during growth. Many methods have been used to reduce the threading dislocation densities in the Ge epitaxial layers (4)(5)(6)(7)(8). Previously, relaxed Ge has been grown by an UHV-CVD system on Si with thick graded Si 1-x Ge x buffer layers.…”

High-Mobility In_0.23Ga_0.77As Channel MOSFETs Grown on Ge/Si Virtual Substrate by MOCVD

“…To achieve high-performance III-V fieldeffect transistors on Si substrate, such as n-type InGaAs MOSFETs [1], inverted-type InGaAs MOS-high-electron mobility transistors (HEMTs) [2], HEMT [3], enhancement mode In 0.7 Ga 0.3 As quantum well (QW) transistor [4], and metal gate semiconductor field effect transistor [5], it is necessary to fabricate high-quality device structures on the Si substrate. Because of the small lattice mismatch (∼0.07%) between GaAs and Ge and progress with the development of Ge growth on the Si substrates [6], [7], Ge is usually used as a buffer layer for the growth of high-quality III-V device structures on the Si substrates [8], [9]. In addition, taking the advantage of the high hole mobility in Ge, the Ge buffer layer could also be used to fabricate pMOSFETs, thus integrating Ge/III-V MOSFETs on the same Si substrate, which could yield a CMOS structure with very high performance [10].…”