Groundbounce in ASIC's: model and test results

Abstract

Groundbounce is the noise produced by simultaneous switching of drivers in an ASIC, due to excessive current draw from the power supply at the time of switching. This noise may cause delay and false triggering problems at the functional level, as well as cause emissions problems due to the fast rise time and amplitude of current spikes induced.The problem of groundbounce has already been considered in the literature [1,2,3], and simple models, such as Vgb = Nss x L x di/dt, have been used to predict the groundbounce voltage level. These models were appropriate for predicting groundbounce in smaller IC's, where all the switching drivers can be assumed to be "clustered" in one area of the chip. In this case, the package inductance (L) from the chip-pads to the package pins is taken as constant, irrespective of the number and position of switching drivers (Nss) within the IC. In larger ASIC's, layout has an important part in determining the value of Nss x L, and we are compelled to introduce the notion of effective number of switching drivers (for a constant inductance), or effective inductance (for a constant number of switching drivers), to better predict groundbounce.The purpose of this paper is threefold: first, present test results which attest to the seriousness of the groundbounce problem in large ASIC's; second, to suggest the importance of the positioning of switching drivers as a factor in reducing groundbounce; third, to refine the model of groundbounce to include layout and package parameters, in order to more accurately calculate the effective inductance value to be used for predictions.Moreover, to the author's knowledge, the correlation between positioning of switching drivers and groundbounce, for a given package and number of switching drivers has not been previously addressed in the literature.The results presented correspond to groundbounce voltages measured in one test chip mounted on a PGA package.

Return path inductance in measurements of package inductance matrixes

“…Ground bounce and power droop can induce signaling errors between a packaged device and the system [7]. A CMOS driver holding low sends the voltage level of the chip ground to the receiver of another device which interprets that level with respect to system ground (or more generally to its own chip ground).…”