Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects

Poulton, John W.; Wilson, John; Chen, Xi; Tell, Stephen G.; Fojtik, Matthew; Greer, Thomas H.; Zimmer, Brian; Song, Sanquan; Nedovic, Nikola; Kudva, Sudhir S.; Sudhakaran, Sunil; Bashirullah, Rizwan; Zhao, Wenxu; Dally, William J.; Gray, C. Thomas

doi:10.1109/cicc.2018.8357077

Cited by 22 publications

(8 citation statements)

References 3 publications

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“…The switched-capacitor charge pump transmitters in the 2:1 MUX shown in Figure 3 have three operating states precharge, positive drive, and negative drive, as shown in Figure 4. 22 During precharge, the driving MOS transistors M0-M3 are turned off, and the precharge MOS transistors M4 and M5 are turned on to charge the charge storage capacitor C s to the supply voltage V DD . During the positive drive, the negative drive MOS transistors M0 and M1 and the precharge MOS transistors M4 and M5 are turned off, and the positive drive MOS transistors M2 and M3 are turned on so that the output of the charge pump circuit is a positive voltage.…”

Section: :1 Muxmentioning

confidence: 99%

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A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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SummaryThis paper proposes a wireline serial link transceiver for on‐package die‐to‐die links based on 12‐nm fin field‐effect transistor (FinFET) technology. The link is crucial for improving the computational performance of larger systems built from chiplets. To achieve high pin/energy efficiency and prevent traditional single‐ended signaling disadvantages, the transceiver adopts single‐ended ground‐reference signaling (GRS) to transfer information. To precompensate for the frequency‐dependent loss, retain the advantages of GRS, and avoid the disadvantages of traditional AC‐coupled equalizer, the transmitter in the transceiver adopts a DC‐coupled switched‐capacitor charge pump equalizer that can transmit GRS and its equilibrium value can be adjusted according to the channel attenuation. This paper proposes a method for timing de‐skew using digital control delay lines to eliminate the timing skew between data and the clock. In addition, this paper presents a duty cycle corrector to avoid duty cycle distortion, with an adjustment range of 44.5% to 52% and a power dissipation of only 30 W. The transceiver has an area of 1.016 0.676 mm2, including one clock lane link and four data lane links. At a nominal 0.8‐V power supply voltage, the aggregate eye‐opening of the measured 25 Gb/s data on an organic substrate channel with an attenuation of −2.2 dB over 6 mm is 0.675 UI, with a bit error rate (BER) of less than 10−12 and an energy efficiency of 1.01 pJ/bit.

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Section: :1 Muxmentioning

confidence: 99%

“…Because F I G U R E 4 Ground-referenced signaling operation. 22 the "instantaneous" DC value continues fluctuating randomly, this effect is known as "DC wander" (or "baseline wander"). 19 To ensure negligible droop, the coupling capacitance should be large enough to minimize DC wander.…”

Section: Transmit Equalizermentioning

confidence: 99%

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

Guo,

Chen,

Wang

et al. 2023

Circuit Theory & Apps

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“…Though, the remainder of this work assumes a conservative projection of a 960MB L3 on an 826mm 2 die, which implies a maximum of 960MB L3 in a 3D COPA-GPU with single MSM die and 1920MB L3 in a 2.5D COPA-GPU with two MSM dies. High Bandwidth 2.5D and 3D Interconnects: High-speed links that enable 2.5D integration are rapidly maturing [16], [19], [43], [71]. Chen et al [16] recently demonstrated 20Gbps signaling rates across a 2.5mm silicon interposer layer at 0.3pJ/b, resulting in a ∼200GB/s/mm bandwidth density per layer, which can be further increased at shorter distances.…”

Section: E Copa-gpu Enabling Technologiesmentioning

confidence: 99%

GPU Domain Specialization via Composable On-Package Architecture

Fu¹,

Bolotin²,

Chatterjee³

et al. 2021

Preprint

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As GPUs scale their low precision matrix math throughput to boost deep learning (DL) performance, they upset the balance between math throughput and memory system capabilities. We demonstrate that converged GPU design trying to address diverging architectural requirements between FP32 (or larger) based HPC and FP16 (or smaller) based DL workloads results in sub-optimal configuration for either of the application domains. We argue that a Composable On-PAckage GPU (COPA-GPU) architecture to provide domain-specialized GPU products is the most practical solution to these diverging requirements. A COPA-GPU leverages multi-chip-module disaggregation to support maximal design reuse, along with memory system specialization per application domain. We show how a COPA-GPU enables DL-specialized products by modular augmentation of the baseline GPU architecture with up to 4× higher off-die bandwidth, 32× larger on-package cache, 2.3× higher DRAM bandwidth and capacity, while conveniently supporting scaled-down HPCoriented designs. This work explores the microarchitectural design necessary to enable composable GPUs and evaluates the benefits composability can provide to HPC, DL training, and DL inference. We show that when compared to a converged GPU design, a DL-optimized COPA-GPU featuring a combination of 16× larger cache capacity and 1.6× higher DRAM bandwidth scales per-GPU training and inference performance by 31% and 35% respectively and reduces the number of GPU instances by 50% in scale-out training scenarios.

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“…In our overall system architecture, we will forward a shared clock for each group of eight optical data channels and use this clock to sample data at the receiver avoiding expensive clock distribution and clock recovery circuits. We have extensively researched similar clock forwarding techniques for short-reach electrical links [27][28][29][30]. This clock forwarding technique allows for very simple transmit circuitry in which the data is serialized, clocked on a common clock, and sent to the modulator driver.…”

Section: Ultra-low Energy Electronicsmentioning

confidence: 99%

PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program) [Invited]

Glick

Abrams

Cheng

et al. 2020

J. Opt. Commun. Netw.

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We review the motivation, goals, and achievements of the Photonic Integrated Networked Energy efficient datacenter (PINE) project, which is part of the Advanced Research Projects Agency-Energy (ARPA-E) ENergyefficient Light-wave Integrated Technology Enabling Networks that Enhance Dataprocessing (ENLITENED) program. The PINE program leverages the unique features of photonic technologies to enable alternative megadatacenters and high-performance computing (HPC) system architectures that deliver more substantial energy efficiency improvements than can be achieved through link energy efficiency alone. In phase 1 of the program, the PINE system architecture demonstrated an average factor of 2.2× improvement in transactions/joule across a diverse set of HPC and datacenter applications. In phase 2, PINE will demonstrate an aggressive 1.0 pJ/bit total link budget with high-bandwidth-density dense wavelength-division multiplexing (DWDM) links to enable additional 2.5× or more efficiency gains through deep resource disaggregation.

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Ground-referenced signaling for intra-chip and short-reach chip-to-chip interconnects

Cited by 22 publications

References 3 publications

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

A 25‐Gb/s/pin ground‐referenced signaling transceiver with a DC‐coupled equalizer for on‐package communication

GPU Domain Specialization via Composable On-Package Architecture

PINE: Photonic Integrated Networked Energy efficient datacenters (ENLITENED Program) [Invited]

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