Grazing incidence ion beams for reducing LER

Struck, C. R M; Neumann, M.; Raju, R.; Bristol, Robert; Ruzic, D. N.

doi:10.1117/12.804692

Cited by 2 publications

(2 citation statements)

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“…Figure 12 shows a comparison of the lithographic performance of an EUV hybrid resist in ''no-bake'', hot-plate PB, and FL PB processes. Aside from this, there are also reports on the use of electron beam (EB) curing, 130) ion implantation, 131,132) and plasma treatment, 133) which have shown an observable decrease in LWR through surface smoothing. Each of these processes has shown smoothening effects for specific roughness frequencies.…”

Section: Post-process Technologiesmentioning

confidence: 99%

Resist Materials and Processes for Extreme Ultraviolet Lithography

Itani¹,

Kozawa

2012

Jpn. J. Appl. Phys.

164

153

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Extreme ultraviolet (EUV) radiation, the wavelength of which is 13.5 nm, is the most promising exposure source for next-generation semiconductor lithography. The development of EUV lithography has been pursued on a worldwide scale. Over the past decade, the development of EUV lithography has significantly progressed and approached its realization. In this paper, the resist materials and processes among the key technologies of EUV lithography are reviewed. Owing to its intensive development, the resist technology has already closely approached the requirements for the 22 nm node. The focus of the development has shifted to the 16 nm node and beyond. Despite the trade-off relationships among resolution, line edge roughness/line width roughness, and sensitivity, the capability of resist technology will go beyond the 16 nm node.

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Section: Post-process Technologiesmentioning

confidence: 99%

Resist Materials and Processes for Extreme Ultraviolet Lithography

Itani¹,

Kozawa

2012

Jpn. J. Appl. Phys.

164

153

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“…Recently, however, with the introduction of lithographically defined thin body devices such as FinFET and Tri-gate FETs, LER started to affect the active region of MOSFETs as well [3,4]. Grazing incidence ion beams [5] and high temperature hydrogen annealing [6] have been proposed to reduce LER, which was shown to result in significant silicon diffusion with LER reduction from ~ 2.8 nm to 0.8 nm. In this work, instead of focusing on reduction of LER itself, we study an electrostatic method to reduce the effects of LER, through the use of a guard-ring gate surrounding the body of the FET.…”

Section: Introductionmentioning

confidence: 99%

Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors

2013

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Accumulated body [1] approach to mitigate the effects of line edge roughness on bulk silicon finFETs and tri-gate FETs is analyzed through 3D TCAD simulations. A side-gate surrounding the body portion of the FET is used to accumulate the body with majority carriers. This approach is predicted to reduce device-to-device variability due to line edge roughness by stronger accumulation of the body in the wider sections of the channel and confinement of the channel away from the edges.

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Grazing incidence ion beams for reducing LER

Cited by 2 publications

References 0 publications

Resist Materials and Processes for Extreme Ultraviolet Lithography

Resist Materials and Processes for Extreme Ultraviolet Lithography

Pentagate Approach to Reduce the Line Edge Roughness Effects in Bulk Si Tri-gate Transistors

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