GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing

Rahman, Shafiur; Abu-Ghazaleh, Nael; Gupta, Rajiv

doi:10.1109/micro50266.2020.00078

Cited by 39 publications

(15 citation statements)

References 55 publications

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“…14, TDGraph-S-without also outperforms Ligra-o on a real platform with a 64-core Intel Xeon Phi 7210 processor and 64 GB main memory, where TDGraph-S-without is the version of TDGraph-S without using the vertex states coalescing strategy. TDGraph-H is also compared with GraphPulse [43] and Jet-Stream [44]. Figure 16 shows that more useless data are prefetched by JetStream than TDGraph-H.…”

Section: Comparison With Software Approachesmentioning

confidence: 99%

“…To alleviate the irregularities in graph processing, GraphDynS [63] employs a hardware/software co-design approach. For efficient asynchronous graph processing, GraphPulse [43] designs a novel event-driven accelerator. Meanwhile, to reduce data movements, GraphPIM [39], GraphP [71], and GraphQ [76] are designed to use the processing-in-memory technique, while GraphR [56] and GaaS-X [13] leverage the massive parallelism of ReRAM.…”

Section: Additional Related Workmentioning

confidence: 99%

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TDGraph

Zhao

Yang

Liao

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

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Many solutions have been recently proposed to support the processing of streaming graphs. However, for the processing of each graph snapshot of a streaming graph, the new states of the vertices affected by the graph updates are propagated irregularly along the graph topology. Despite the years' research efforts, existing approaches still suffer from the serious problems of redundant computation overhead and irregular memory access, which severely underutilizes a many-core processor. To address these issues, this paper proposes a topology-driven programmable accelerator TDGraph, which is the first accelerator to augment the many-core processors to achieve high performance processing of streaming graphs. Specifically, we propose an efficient topology-driven incremental execution approach into the accelerator design for more regular state propagation and better data locality. TDGraph takes the vertices affected by graph updates as the roots to prefetch other vertices along the graph topology and synchronizes the incremental computations of them on the fly. In this way, most state propagations originated from multiple vertices affected by different graph updates can be conducted together along the graph topology, which help reduce the redundant computations and data access cost. Besides, through the efficient coalescing of the accesses to vertex states, TDGraph further improves the utilization of the cache and memory bandwidth. We have evaluated TDGraph on a simulated 64-core processor. The results show that, the state-of-the-art software system achieves the speedup of 7.1∼21.4 times after integrating with TDGraph, while incurring only 0.73% area cost. Compared with four cutting-edge accelerators, i.e., HATS, Minnow, PHI, and DepGraph, TDGraph gains the speedups of 4.6∼12.7, 3.2∼8.6, 3.8∼9.7, and 2.3∼6.1 times, respectively.

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Section: Comparison With Software Approachesmentioning

confidence: 99%

Section: Additional Related Workmentioning

confidence: 99%

TDGraph

Zhao

Yang

Liao

et al. 2022

Proceedings of the 49th Annual International Symposium on Computer Architecture

View full text Add to dashboard Cite

show abstract

“…to a growing number of specialized hardware blocks [40,70]. A multitude of accelerators have been designed for many different application domains [12,17,31,39,47,60,62,65,66,76,81,86,90].…”

Section: Introductionmentioning

confidence: 99%

Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs

Zuckerman,

Giri,

Kwon

et al. 2021

Preprint

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One of the most critical aspects of integrating loosely-coupled accelerators in heterogeneous SoC architectures is orchestrating their interactions with the memory hierarchy, especially in terms of navigating the various cache-coherence options: from accelerators accessing off-chip memory directly, bypassing the cache hierarchy, to accelerators having their own private cache. By running realsize applications on FPGA-based prototypes of many-accelerator multi-core SoCs, we show that the best cache-coherence mode for a given accelerator varies at runtime, depending on the accelerator's characteristics, the workload size, and the overall SoC status.Cohmeleon applies reinforcement learning to select the best coherence mode for each accelerator dynamically at runtime, as opposed to statically at design time. It makes these selections adaptively, by continuously observing the system and measuring its performance. Cohmeleon is accelerator-agnostic, architectureindependent, and it requires minimal hardware support. Cohmeleon is also transparent to application programmers and has a negligible software overhead. FPGA-based experiments show that our runtime approach offers, on average, a 38% speedup with a 66% reduction of off-chip memory accesses compared to state-of-the-art design-time approaches. Moreover, it can match runtime solutions that are manually tuned for the target architecture. CCS CONCEPTS• Computer systems organization → System on a chip; Reconfigurable computing; Heterogeneous (hybrid) systems; • Computing methodologies → Reinforcement learning.

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“…As a result, the accelerators mainly focus on improving memory access efficiency, hiding communication latency, and/or reducing load imbalance. Recently, several domain-specific architectures are developed for graph computation, including Processing-In-Memory (PIM) based architectures [8], [46], [55], [57], accelerator for asynchronous [36], [51], [52] and iterative [38] graph processing.…”

Section: Introductionmentioning

confidence: 99%

IntersectX: An Efficient Accelerator for Graph Mining

Rao¹,

Chen²,

Yik³

et al. 2020

Preprint

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Graph mining applications try to find all embeddings that match specific patterns. Compared to the traditional graph computation, graph mining applications are computationintensive. The state-of-the-art method, pattern enumeration, specifically constructs the embeddings that satisfy the pattern, leading to significant speedups over the exhaustive check method. However, the key operation intersection poses challenges to conventional architectures and takes substantial execution time.In this paper, we propose IntersectX, a vertical approach to accelerate graph mining with stream instruction set extension and architectural supports based on conventional processor. The stream based ISA can considered as a natural extension to the traditional instructions for ordinary scalar values. We develop the IntersectX architecture composed of specialized mechanisms that efficiently implement the stream ISA extensions, including:(1) Stream Mapping Table (SMT) that records the mapping between stream ID and stream register; (2) the Stream Cache (S-Cache) that enables efficient stream data movements; (3) tracking the dependency between streams with a property of intersection; (4) Stream Value Processing Unit (SVPU) that implements sparse value computations; and (5) the nested intersection translator that generates micro-op sequences for implementing nested intersections. We implement IntersectX ISA and architecture on zsim [42]. We use 7 popular graph mining applications (triangle/three-chain/tailed-traingle counting, 3-motif mining, 4/5-clique counting, and FSM) on 10 real graphs. Our experiments show that IntersectX significantly outperforms our CPU baseline and GRAMER, a state-of-the-art graph mining accelerator. IntersectX's speedups over the CPU baseline and GRAMER [53] are on average 10.7×and 40.1×(up to 83.9×and 181.8×), respectively.

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GraphPulse: An Event-Driven Hardware Accelerator for Asynchronous Graph Processing

Cited by 39 publications

References 55 publications

TDGraph

TDGraph

Cohmeleon: Learning-Based Orchestration of Accelerator Coherence in Heterogeneous SoCs

IntersectX: An Efficient Accelerator for Graph Mining

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