GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition

Zhang, Mingxing; Zhuo, Youwei; Wang, Chao; Gao, Mingyu; Wu, Yongwei; Chen, Kang; Kozyrakis, Christos; Qian, Xuehai

doi:10.1109/hpca.2018.00053

Cited by 159 publications

(99 citation statements)

References 29 publications

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“…Source-Oriented [15,27,69,[77][78][79][80] Destination-Oriented [16,26,30,73,81] Grid [28,70,82] Heuristic [29,31,32,75,76,83,84] Source-oriented Partition. it is convenient to determine the partitions that need the updated vertex property in the graph processing.…”

Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

“…Low-latency high-bandwidth scratchpad memory can be fully utilized. GraphP [81] also applies this partition.…”

Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

“…Besides, graphs are processed in a distributed manner between HMCs. Vertex-cut partitioning is also used to reduce the communication cost between HMCs [73,81] .…”

Section: Asic-based Designsmentioning

confidence: 99%

“…Tesseract [32] designs the remote function call mecha- Partitioning methods and coalescing methods are usually needed to reduce the number of messages [81] . Besides, extra memory copying operations and buffers are also needed.…”

Section: Communication Modelmentioning

confidence: 99%

See 3 more Smart Citations

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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Graph is a well known data structure to represent the associated relationships in a variety of applications, e.g., data science and machine learning. Despite a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures, dedicated hardware solutions, also referred to as graph processing accelerators, are essential and emerging to provide the benefits significantly beyond those pure software solutions can offer. In this paper, we conduct a systematical survey regarding the design and implementation of graph processing accelerator. Specifically, we review the relevant techniques in three core components toward a graph processing accelerator: preprocessing, parallel graph computation and runtime scheduling. We also examine the benchmarks and results in existing studies for evaluating a graph processing accelerator. Interestingly, we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and complexity of hardware configurations. We finially present to discuss several challenges in details, and to further explore the opportunities for the future research.

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Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

“…Low-latency high-bandwidth scratchpad memory can be fully utilized. GraphP [81] also applies this partition.…”

Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

“…Besides, graphs are processed in a distributed manner between HMCs. Vertex-cut partitioning is also used to reduce the communication cost between HMCs [73,81] .…”

Section: Asic-based Designsmentioning

confidence: 99%

Section: Communication Modelmentioning

confidence: 99%

See 2 more Smart Citations

A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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show abstract

“…The essential way to improve the performance of large-scale graph processing and overcome the "memory wall" for big data problems is to provide a high bandwidth of data access. Thus, these graph processing accelerators usually integrated multiple processing units "closer" to the memory, including using on-chip eDRAM [11], on-chip SRAM [6,23], emerging 3D-stacked memory [1,7,27], etc. Such designs can achieve magnitudes of speedup against graph processing systems on conventional architectures [4,10,18,21,22,25,[28][29][30].…”

Section: Introductionmentioning

confidence: 99%

GraphIA

Dai

et al. 2018

Proceedings of the International Symposium on Memory Systems

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Graph processing is widely used in various domains, while processing large-scale graphs has always been memory-bound. In-situ processing is a promising solution to overcome the "memory wall" challenges in such memory-intensive applications. Previous accelerator designs for graph processing only focused on integrating more computing units inside memories or using more memory layers, rather than exploiting the huge parallelism lying in memory banks. In this paper, we present GraphIA, an In-situ Accelerator for large-scale graph processing based on DRAM technology. GraphIA couples large-capacity memory and computing resource in DRAM by connecting multiple chips with computation circuits inside. GraphIA chips are organized into a scaling ring interconnection, which is able to maximize the individual bandwidth with minimal connection overheads and scale to larger graphs by using more chips. Banks in DRAM are organized into heterogeneous edge and vertex banks, cooperating with customized peripheral circuits. Data duplication and scheduling schemes in heterogeneous banks are further introduced to overcome the performance loss caused by the irregular local and remote memory access in our multi-chip ring structure, achieving 1.63× and 1.16× speedup respectively. According to our extensive experiments, by adopting GraphIA design, our in-situ accelerator achieves 217× speedup CPU-DRAM designs. CCS CONCEPTS• Computer systems organization → Processors and memory architectures; • Hardware → Memory and dense storage;

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Cost‐efficient and network‐aware dynamic repartitioning‐based algorithms for scheduling large‐scale graphs in cloud computing environments

Heidari

Buyya

2018

Softw Pract Exp

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Large amount of data that is generated by Internet and enterprize applications are stored in the form of graphs. Graph processing systems are broadly used in enterprizes to process such data. With the rapid growth in mobile and social applications and complicated connections of Internet websites, massive concurrent operations need to be handled. On the other hand, the intrinsic structure and the size of real-world graphs make distributed processing of graphs more challenging. Low balanced communication and computation, low preprocessing overhead, low memory footprint, and scalability should be offered by distributed graph analytics frameworks. Moreover, the effects of network factors such as bandwidth and traffic as well as monetary cost of processing such large-scale graphs and the mutual impact of these elements have been less studied. To address these issues, we proposed two dynamic repartitioning algorithms that consider network factors, affecting public cloud environments to decrease the monetary cost of processing. A new classification of graph algorithms and processing is also introduced, which will be used to choose the best strategy for processing at any operation. We plugged these algorithms to our extended graph processing system (iGiraph) and compared them with those supported in other graph processing systems such as Giraph and Surfer on Australian National Cloud Infrastructure. We observed that up to 30% faster execution time, up to 50% network traffic decline, and more than 50% cost reduction are achieved by our algorithms compared to a framework such as the popular Giraph.

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GraphP: Reducing Communication for PIM-Based Graph Processing with Efficient Data Partition

Cited by 159 publications

References 29 publications

A Survey on Graph Processing Accelerators: Challenges and Opportunities

A Survey on Graph Processing Accelerators: Challenges and Opportunities

GraphIA

Cost‐efficient and network‐aware dynamic repartitioning‐based algorithms for scheduling large‐scale graphs in cloud computing environments

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