GRAPHOPT: constrained-optimization-based parallelization of irregular graphs

Shah, Nimish; Meert, Wannes; Verhelst, Marian

doi:10.48550/arxiv.2105.01976

Cited by 2 publications

(7 citation statements)

References 43 publications

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“…2(a) shows a common approach for accelerating DAGs, in which a DAG is partitioned into smaller subgraphs that can be executed on parallel cores, e.g, in a multicore CPU. This approach is used in works like [39], [44], [46]. The cores have to synchronize occasionally for race-free communication that happens through a shared memory structure like an L3 cache in CPUs or a shared scratchpad in [46].…”

Section: A Making Irregular Data Accesses Predictablementioning

confidence: 99%

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DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

Shah

Meert

Verhelst

2022

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

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A growing number of applications like probabilistic machine learning, sparse linear algebra, robotic navigation, etc., exhibit irregular data flow computation that can be modeled with directed acyclic graphs (DAGs). The irregularity arises from the seemingly random connections of nodes, which makes the DAG structure unsuitable for vectorization on CPU or GPU. Moreover, the nodes usually represent a small number of arithmetic operations that cannot amortize the overhead of launching tasks/kernels for each node, further posing challenges for parallel execution.To enable energy-efficient execution, this work proposes DAG processing unit (DPU) version 2, a specialized processor architecture optimized for irregular DAGs with static connectivity. It consists of a tree-structured datapath for efficient data reuse, a customized banked register file, and interconnects tuned to support irregular register accesses. DPU-v2 is utilized effectively through a targeted compiler that systematically maps operations to the datapath, minimizes register bank conflicts, and avoids pipeline hazards. Finally, a design space exploration identifies the optimal architecture configuration that minimizes the energy-delay product. This hardwaresoftware co-optimization approach results in a speedup of 1.4×, 3.5×, and 14× over a state-of-the-art DAG processor ASIP, a CPU, and a GPU, respectively, while also achieving a lower energy-delay product. In this way, this work takes an important step towards enabling an embedded execution of emerging DAG workloads.

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Section: A Making Irregular Data Accesses Predictablementioning

confidence: 99%

“…• Due to the irregular structure, parallelizing different parts of DAGs across multiple units (like CPU cores, GPU streaming multiprocessors, etc.) demands high communication and synchronization overhead, limiting the parallelization benefits [44].…”

Section: Introductionmentioning

confidence: 99%

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

Shah

Meert

Verhelst

2022

2022 55th IEEE/ACM International Symposium on Microarchitecture (MICRO)

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“…DPU uses an advanced graph-partitioning technique to reduce the number of synchronization barriers, as explained in [10]. The DAGs are partitioned into superlayers (fig.…”

Section: A Background Of Dag Executionmentioning

confidence: 99%

“…The CUs communicate via a global The detailed architecture of CU is explained later in §IV. A specialized compiler [10] is designed that takes an arbitrary DAG and generates the superlayers, schedules operations, performs memory allocation, etc. for DPU execution.…”

Section: A Compute Units (Cu)mentioning

confidence: 99%

“…CPU: An Intel(R) Xeon Gold 6154 CPU operating at 3GHz is used for comparison. For PC, a standard Julia-based library called Juice [30] (CPU-JUICE) and an highly-optimized OpenMP-based implementation [10] (CPU-OMP) are used for comparison. The SpTRSV performance is evaluated with the standard Intel Math Kernel Library (MKL v2021.1).…”

Section: Comparison With Cpu and Gpumentioning

confidence: 99%

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DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm

Shah,

Olascoaga,

Zhao

et al. 2021

Preprint

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Computation in several real-world applications like probabilistic machine learning, sparse linear algebra, and robotic navigation, can be modeled as irregular directed acyclic graphs (DAGs). The irregular data dependencies in DAGs pose challenges to parallel execution on general-purpose CPUs and GPUs, resulting in severe under-utilization of the hardware. This paper proposes DPU, a specialized processor designed for the efficient execution of irregular DAGs. The DPU is equipped with parallel compute units that execute different subgraphs of a DAG independently. The compute units can synchronize within a cycle using a hardware-supported synchronization primitive, and communicate via an efficient interconnect to a global banked scratchpad. Furthermore, a precision-scalable posit TM arithmetic unit is developed to enable application-dependent precision. The DPU is taped-out in 28nm CMOS, achieving a speedup of 5.1× and 20.6× over state-of-the-art CPU and GPU implementations on DAGs of sparse linear algebra and probabilistic machine learning workloads. This performance is achieved while operating at a power budget of 0.23W, as opposed to 55W and 98W of the CPU and GPU, resulting in a peak efficiency of 538 GOPS/W with DPU, which is 1350× and 9000× higher than the CPU and GPU, respectively. Thus, with specialized architecture, DPU enables low-power execution of irregular DAG workloads.

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GRAPHOPT: constrained-optimization-based parallelization of irregular graphs

Cited by 2 publications

References 43 publications

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

DPU-v2: Energy-efficient execution of irregular directed acyclic graphs

DPU: DAG Processing Unit for Irregular Graphs with Precision-Scalable Posit Arithmetic in 28nm

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