Graphical optimization method applied to a 6 GHz single-ended ring oscillators

Gargouri, Nadia; Hajri, Madiha; Issa, Dalenda Ben; Kachouri, Abdennaceur; Samet, Mounir

doi:10.1109/sta.2015.7505191

Cited by 2 publications

(1 citation statement)

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“…A new design of oscillator with process, voltage and temperature tolerant circuit achieves goof frequency of oscillation but it has very less FOM [24]. In the differential CSVCO circuit, achieves better oscillation frequency but suffers from maximum leakage power [25], [26]. A dual mode time interleaved ring VCO is utilized for high performance radio frequency (RF) systems.…”

Section: Introductionmentioning

confidence: 99%

Design and analysis of 7-stage MOS current mode logic power gated MOSFETs in current starved voltage-controlled oscillator for the phase locked loop application

Madheswaran,

Panneerselvam

2024

IJECE

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This paper presents a new process, voltage and temperature (PVT) tolerant 7-stage ring type current starved voltage-controlled oscillator (CS-VCO). In this, a 7-stage ring VCO is proposed using power gated technique for phase locked loop (PLL) application. PLL plays a major role in clock and data recovery, Global Positioning System (GPS) system and satellite communications. For the high-speed application of PLL it is designed using 7-stage inverter delay cell with MOS current mode logic (MCML) technique. The circuit undergoes process, voltage and temperature variations with different parameters such as average power, oscillation frequency, phase noise, tuning range and output noise. The Monte-Carlo analysis justifies the proposed design provides better results. The circuit is simulated under 45 nm CMOS technology using cadence virtuoso. The average power consumption of the proposed circuit is 29.368 µW with the oscillation frequency of 3.06 GHz. The output noise and the phase noise of the proposed VCO are -161.55 dB and -125.92 dBc/Hz respectively. It achieves the frequency tuning range (FTR) of 95.09%. The obtained simulation results are highly robust with PVT making the circuit suitable for PLL application.

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Section: Introductionmentioning

confidence: 99%