GraphH: A Processing-in-Memory Architecture for Large-Scale Graph Processing

Dai, Guohao; Huang, Tianhao; Chi, Yuze; Zhao, Jishen; Sun, Guangyu; Liu, Yongpan; Wang, Yu; Xie, Yuan; Yang, Huazhong

doi:10.1109/tcad.2018.2821565

Cited by 112 publications

(111 citation statements)

References 24 publications

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“…The basic idea is to sort the edges based on either the source vertex indices or the destination vertex indices. Sorting the edges in an as-cending manner generally improves the data locality because the neighboring vertex property can be prefetched and probably reused [73] . In the graph processing, source vertex property will be read and destination vertex property will be updated accordingly.…”

Section: Graph Orderingmentioning

confidence: 99%

“…Source-Oriented [15,27,69,[77][78][79][80] Destination-Oriented [16,26,30,73,81] Grid [28,70,82] Heuristic [29,31,32,75,76,83,84] Source-oriented Partition. it is convenient to determine the partitions that need the updated vertex property in the graph processing.…”

Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

“…Besides, graphs are processed in a distributed manner between HMCs. Vertex-cut partitioning is also used to reduce the communication cost between HMCs [73,81] .…”

Section: Asic-based Designsmentioning

confidence: 99%

“…HMCs not only provide the capability of processing in memory but also scale well. The cost on communications among different HMC cubes dominates the performance [32,73,81] . GraphP [81] utilizes a source-cut partitioning method to significantly reduce the communication overhead.…”

Section: ) Multiple Accelerators Extensionmentioning

confidence: 99%

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A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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Graph is a well known data structure to represent the associated relationships in a variety of applications, e.g., data science and machine learning. Despite a wealth of existing efforts on developing graph processing systems for improving the performance and/or energy efficiency on traditional architectures, dedicated hardware solutions, also referred to as graph processing accelerators, are essential and emerging to provide the benefits significantly beyond those pure software solutions can offer. In this paper, we conduct a systematical survey regarding the design and implementation of graph processing accelerator. Specifically, we review the relevant techniques in three core components toward a graph processing accelerator: preprocessing, parallel graph computation and runtime scheduling. We also examine the benchmarks and results in existing studies for evaluating a graph processing accelerator. Interestingly, we find that there is not an absolute winner for all three aspects in graph acceleration due to the diverse characteristics of graph processing and complexity of hardware configurations. We finially present to discuss several challenges in details, and to further explore the opportunities for the future research.

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Section: Graph Orderingmentioning

confidence: 99%

Section: Partitioning Schemes Graph Acceleratorsmentioning

confidence: 99%

“…Besides, graphs are processed in a distributed manner between HMCs. Vertex-cut partitioning is also used to reduce the communication cost between HMCs [73,81] .…”

Section: Asic-based Designsmentioning

confidence: 99%

Section: ) Multiple Accelerators Extensionmentioning

confidence: 99%

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A Survey on Graph Processing Accelerators: Challenges and Opportunities

Gui

Zheng

et al. 2019

J. Comput. Sci. Technol.

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“…The essential way to improve the performance of large-scale graph processing and overcome the "memory wall" for big data problems is to provide a high bandwidth of data access. Thus, these graph processing accelerators usually integrated multiple processing units "closer" to the memory, including using on-chip eDRAM [11], on-chip SRAM [6,23], emerging 3D-stacked memory [1,7,27], etc. Such designs can achieve magnitudes of speedup against graph processing systems on conventional architectures [4,10,18,21,22,25,[28][29][30].…”

Section: Introductionmentioning

confidence: 99%

GraphIA

Dai

et al. 2018

Proceedings of the International Symposium on Memory Systems

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Graph processing is widely used in various domains, while processing large-scale graphs has always been memory-bound. In-situ processing is a promising solution to overcome the "memory wall" challenges in such memory-intensive applications. Previous accelerator designs for graph processing only focused on integrating more computing units inside memories or using more memory layers, rather than exploiting the huge parallelism lying in memory banks. In this paper, we present GraphIA, an In-situ Accelerator for large-scale graph processing based on DRAM technology. GraphIA couples large-capacity memory and computing resource in DRAM by connecting multiple chips with computation circuits inside. GraphIA chips are organized into a scaling ring interconnection, which is able to maximize the individual bandwidth with minimal connection overheads and scale to larger graphs by using more chips. Banks in DRAM are organized into heterogeneous edge and vertex banks, cooperating with customized peripheral circuits. Data duplication and scheduling schemes in heterogeneous banks are further introduced to overcome the performance loss caused by the irregular local and remote memory access in our multi-chip ring structure, achieving 1.63× and 1.16× speedup respectively. According to our extensive experiments, by adopting GraphIA design, our in-situ accelerator achieves 217× speedup CPU-DRAM designs. CCS CONCEPTS• Computer systems organization → Processors and memory architectures; • Hardware → Memory and dense storage;

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