2022
DOI: 10.1109/tpel.2022.3157873
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Graph-Model-Based Generative Layout Optimization for Heterogeneous SiC Multichip Power Modules With Reduced and Balanced Parasitic Inductance

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Cited by 17 publications
(6 citation statements)
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“…The minimum cut represents the border between upper and lower control levels. In power electronics, graph theory has been used for dynamic analysis [18], [19] (using switching flow graphs), cooperative control [20] (using directed communication graphs), converter topology simplification [21] (using node merging and path elimination), converter topology derivation [22] (using graph search), and chip layout optimization [23] (using constraint graphs). Another prominent example of using the minimum cut -maximum flow theorem is image segmentation.…”
Section: Graph Partitioning Methodsmentioning
confidence: 99%
“…The minimum cut represents the border between upper and lower control levels. In power electronics, graph theory has been used for dynamic analysis [18], [19] (using switching flow graphs), cooperative control [20] (using directed communication graphs), converter topology simplification [21] (using node merging and path elimination), converter topology derivation [22] (using graph search), and chip layout optimization [23] (using constraint graphs). Another prominent example of using the minimum cut -maximum flow theorem is image segmentation.…”
Section: Graph Partitioning Methodsmentioning
confidence: 99%
“…(i) Component-level: In [20], a graph model is constructed to represent the complex, heterogeneous layouts of multichip silicon carbide power modules, capturing interconnectivity and design constraints, and using this model in conjunction with integer programming and genetic algorithms for systematic and efficient optimization of module layouts. In the latest framework of design automation technique PowerSynth 2 [59], constraint graphs are constructed to enable bottom-up constraint propagation for synthesizing layouts that respond to various design constraints, such as minimum width, enclosure, and spacing between components, leading to optimized and constraint-aware solutions.…”
Section: B Recent Developmentsmentioning
confidence: 99%
“…In this context, Graph Theory has emerged as a promising tool for addressing these challenges, especially in recent years [2]. Serving as a common language among various disciplines, graph theory can be leveraged as a powerful tool to enable systematic modelling and analysis [3][4][5][6][7], design new converters [8][9][10][11][12], control their operations [13,14], estimate and identify potential issues [15][16][17], optimize the systems [18][19][20], or even facilitate the understanding of the interconnections and interactions between components in power-electronics-based systems [21][22][23]. Especially in recent years, innovative research keeps emerging, covering component-level, converter-level and system-level of power electronics [24][25][26][27][28][29][30][31][32][33][34][35][36][37].…”
Section: Introductionmentioning
confidence: 99%
“…53,54 In the literature, many works can be found in which attempts to solve the aforementioned problems are described through solutions that are mainly based on reducing the negative effects of parasite inductances in discrete devices [55][56][57][58] or power modules (embedded bare dies). [59][60][61][62] Taking into account the new trends and technical requirements on this topic (in addition to others such as efficiency, losses, power density, cost, and size-weight ratio), the main features of power modules and discrete devices are explained in this review. At this point, the benefits of using power modules compared to discrete devices are highlighted, summarizing the main solutions for the electric vehicle.…”
Section: Introductionmentioning
confidence: 99%
“…For this reason, the leap from silicon technology to other semiconductors derived from WBG materials can cause some problems such as oscillations and electromagnetic interferences (EMI), 49,50 higher harmonic content, 51 cross‐talk effects, 52 and the effect of overvoltages on semiconductor shutdown 53,54 . In the literature, many works can be found in which attempts to solve the aforementioned problems are described through solutions that are mainly based on reducing the negative effects of parasite inductances in discrete devices 55‐58 or power modules (embedded bare dies) 59‐62 . Taking into account the new trends and technical requirements on this topic (in addition to others such as efficiency, losses, power density, cost, and size‐weight ratio), the main features of power modules and discrete devices are explained in this review.…”
Section: Introductionmentioning
confidence: 99%