GPU register file virtualization

Abstract

To support massive number of parallel thread contexts, Graphics Processing Units (GPUs) use a huge register file, which is responsible for a large fraction of GPU's total power and area. The conventional belief is that a large register file is inevitable for accommodating more parallel thread contexts, and technology scaling makes it feasible to incorporate ever increasing size of register file. In this paper, we demonstrate that the register file size need not be large to accommodate more threads context. We first characterize the useful lifetime of a register and show that register lifetimes vary drastically across various registers that are allocated to a kernel. While some registers are alive for the entire duration of the kernel execution, some registers have a short lifespan. We propose GPU register file virtualization that allows multiple warps to share physical registers. Since warps may be scheduled for execution at different points in time, we propose to proactively release dead registers from one warp and re-allocate them to a different warp that may occur later in time, thereby reducing the needless demand for physical registers. By using register virtualization, we shrink the architected register space to a smaller physical register space. By under-provisioning the physical register file to be smaller than the architected register file we reduce dynamic and static power consumption. We then develop a new register throttling mechanism to run applications that exceed the size of the under-provisioned register file without any deadlock. Our evaluation shows that even after halving the architected register file size using our proposed GPU register file virtualization applications run successfully with negligible performance overhead.

Haws

“…In HAWS execution, when instructions retire, we use register renaming to avoid WARs and WAWs when storing results, as necessary. Registers files in the GPU are underutilized in many applications, which has been discussed in many recent studies [7,8,16]. Based on these studies and our evaluation, we propose to use the underutilized registers for register renaming.…”

A Framework for Automated and Controlled Floating-Point Accuracy Reduction in Graphics Applications on GPUs

“…In this section we evaluate how the register widths affect what needs to be stored in the register file at any given time during the lifetime of the kernel. Studying the amount that register pressure can be reduced at all instructions (and not just the maximum register pressure) can be interesting for, for instance, power optimizations such as shutting down unused banks [12] or for performance optimizations such as sharing unused physical registers [7].…”

“…GPU register file optimizations. Register file optimization techniques targeting GPUs include a method which compresses the register file data using BDI [12], virtualization of the register file [7], and a partitioned register file that places rarely accessed registers in a lowenergy, high-latency register bank [1]. All of these approaches target power efficiency rather than performance efficiency, and none of them exploit approximations.…”

Split Latency Allocator: Process Variation-Aware Register Access Latency Boost in a Near-Threshold Graphics Processing Unit

“…Jeon et al presented a register file virtualization technique to reduce the physical area as well as power consumption of architected register files [5]. In the second category, Liang et al proposed variable latency register files to mitigate the effects of process variation in CPUs [9].…”

“…A huge register file is required to maintain the latency-hiding ability. Therefore the register file becomes a potential soft target for PV [5]. The most prominent manifestation of PV in GPU register files is the variability in the access latency.…”