GPU-accelerated static timing analysis

Guo, Zizheng; Huang, Tsung‐Wei; Lin, Yibo

doi:10.1145/3400302.3415631

Cited by 42 publications

(7 citation statements)

References 21 publications

(63 reference statements)

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“…At a particular VLSI timing analysis example, Heteroflow can reduce a baseline runtime from 99 minutes to 13 minutes (7.7× speed-up) on a machine of 40 CPU cores and 4 GPUs. Future work will focus on distributing our scheduler based on [46] and incorporating a broader range of workloads, including machine learning [47], [48] and engineering simulation [49], [50], [51].…”

Section: Discussionmentioning

confidence: 99%

Concurrent CPU-GPU Task Programming using Modern C++

Huang¹,

Lin²

2022

Preprint

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In this paper, we introduce Heteroflow, a new C++ library to help developers quickly write parallel CPU-GPU programs using task dependency graphs. Heteroflow leverages the power of modern C++ and task-based approaches to enable efficient implementations of heterogeneous decomposition strategies. Our new CPU-GPU programming model allows users to express a problem in a way that adapts to effective separation of concerns and expertise encapsulation. Compared with existing libraries, Heteroflow is more cost-efficient in performance scaling, programming productivity, and solution generality. We have evaluated Heteroflow on two real applications in VLSI design automation and demonstrated the performance scalability across different CPU-GPU numbers and problem sizes. At a particular example of VLSI timing analysis with million-scale tasking, Heteroflow achieved 7.7× runtime speed-up (99 vs 13 minutes) over a baseline on a machine of 40 CPU cores and 4 GPUs.

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Section: Discussionmentioning

confidence: 99%

Concurrent CPU-GPU Task Programming using Modern C++

Huang¹,

Lin²

2022

Preprint

Self Cite

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“…Chan et al used machine learning algorithms to evaluate the timing slacks of embedded SRAM [13]. Guo et al propose an efficient implementation for accelerating STA on a GPU and implemented their algorithms on top of OpenTimer, which achieve up to 3.69× speed-up on a large design of 1.6 M gates and 1.6 M nets using one GPU [14].…”

Section: Related Workmentioning

confidence: 99%

Machine-Learning-Based Multi-Corner Timing Prediction for Faster Timing Closure

et al. 2022

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For the purpose of fixing timing violations, static timing analysis (STA) of full-corners is repeatedly executed, which is time-consuming. Given a timing path, timing results at some corners (“dominant corners”) are utilized to predict timing at other corners (“non-dominant corners”), which can greatly shorten the runtime of STA. However, the huge number of combinations of the dominant corners and the wide difference in prediction accuracy make it difficult to apply multi-corner timing prediction to chip industrial design. In this paper, we propose a dominant corner selection strategy to quickly determine the dominant corner combination with high prediction accuracy, along with which a new multi-corner timing prediction process is established to speed up STA. Experimental results show that our method can not only effectively accelerate STA, but also ensure the high prediction accuracy of the prediction timing. On the public ITC’99 benchmark, the prediction accuracy of the dominant corner combination selected by the proposed method is up to 98.2%, which is an improvement of 15% compared to the state-of-the-art method. For industrial application, we apply our method by using timing results on only 2 dominant corners to predict the other 12 non-dominant corners, which accelerates the runtime of the timing closure process by more than 2×.

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“…(1,1) at iteration 2 is computed using the data from its neighboring cells in the yellow area at iteration 1. This can be repeated for other cells at iteration 2, like cell 2 (3,1) which is computed in parallel to cell 2 (1,1) . Iteration-Parallelism.…”

Section: An Stencil Multi-fpga Pipelinementioning

confidence: 99%

“…With the limits imposed by the power density of semiconductor technology, heterogeneous systems became a design alternative that combines CPUs with domain-specific accelerators to improve power-performance efficiency [1]. A modern heterogeneous system typically combines general-purpose CPUs and GPUs to speedup complex scientific applications [2]. However, for many specialized applications that can benefit from pipelined parallelism (e.g.…”

Section: Introductionmentioning

confidence: 99%

Enabling OpenMP Task Parallelism on Multi-FPGAs

Nepomuceno

Sterle

Valarini

et al. 2021

2021 IEEE 29th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM)

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FPGA-based hardware accelerators have received increasing attention mainly due to their ability to accelerate deep pipelined applications, thus resulting in higher computational performance and energy efficiency. Nevertheless, the amount of resources available on even the most powerful FPGA is still not enough to speed up very large modern workloads. To achieve that, FPGAs need to be interconnected in a Multi-FPGA architecture capable of accelerating a single application. However, programming such architecture is a challenging endeavor that still requires additional research. This paper extends the OpenMP task-based computation offloading model to enable a number of FPGAs to work together as a single Multi-FPGA architecture. Experimental results for a set of OpenMP stencil applications running on a Multi-FPGA platform consisting of 6 Xilinx VC709 boards interconnected through fiber-optic links have shown close to linear speedups as the number of FPGAs and IP-cores per FPGA increase.

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GPU-accelerated static timing analysis

Cited by 42 publications

References 21 publications

Concurrent CPU-GPU Task Programming using Modern C++

Concurrent CPU-GPU Task Programming using Modern C++

Machine-Learning-Based Multi-Corner Timing Prediction for Faster Timing Closure

Enabling OpenMP Task Parallelism on Multi-FPGAs

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