GPCAD: a tool for CMOS op-amp synthesis

Abstract

We present a method for optimizing and automating component and transistor sizing for CMOS operational amplifiers. We observe that a wide variety of performance measures can be formulated as posynomial functions of the design variables. As a result, amplifier design problems can be formulated as a geometric program, a special type of convex optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected.After briefly introducing the method, which is described in more detail in [1], we show how the method can be applied to six common op-amp architectures, and give several example designs.

Digital Circuit Optimization via Geometric Programming

“…Other problems in digital circuit design where GP plays a role include buffering and wire sizing Wong 1999, 2001a), sizing and placement (Chen et al 2000), yield maximization , Patil et al 2005, parasitic reduction (Qin and Cheng 2003), clock tree design (Vittal and Marek-Sadowska 1997), and routing (Borah et al 1997). Geometric programming has also been used for the design of nondigital circuits, e.g., analog circuits (Dawson et al 2001, Hershenson 2003, Hershenson et al 1998, Mandal and Visvanathan 2001, Vanderhaegen and Brodersen 2004, mixed-signal circuits (Colleran et al 2003, Hassibi and Hershenson 2002, Hershenson 2002, and RF (radio frequency) circuits Mohan et al 1999Mohan et al , 2000Xu et al 2004). Geometric programming has also been used in floorplanning, for both analog and digital circuits (Moh et al 1996).…”

An algorithm for exploiting modeling error statistics to enable robust analog optimization

“…Most standard equation-based optimization flows that have been proposed rely on a sequence of basic steps in setting up the optimization [6], [8], [10]. First, the simulation data generated by SPICE are used to fit the parameters of each transistor, using linear least-squares regression.…”

“…While in part, this is due to the complex device physics, another important source of error is due to the limitations imposed by the requirement of modeling in a GP-compatible manner. In addition to limiting our fitting capability, GP-compatibility forces us to eliminate referencing some key input variables, e.g., it has been proven difficult to capture the dependence on V ds (drain to source voltage) in posynomial form, in contrast to dependence on I (drain current), W (width), and L (gate length) [6]. As a result, the optimization model may differ greatly from the behavior of the physical device.…”

“…The existing work has fallen into two major categories based on how they evaluate a solution point to drive optimization: approaches relying on extensive use of SPICE simulations [11], [12], [9], and those that construct an analytical model of circuit behavior and use the model to drive the optimization [5], [10], [13], [6]. Clearly, evaluating a solution point via a SPICE simulation gives the most accurate measure of the feasibility and optimality of a solution.…”

“…In [8], the proposal to model transistor parameter behavior using piecewise linear models improves accuracy, but may lead to non-posynomial constraints, hence rendering convex optimization unusable. Elsewhere in the literature, the modeling error is either fully ignored [6], or local refinement methods are used [10], or generic robustification strategies are adopted [8] that robustify the optimization, but, crucially, not in a way directly linked to the errors in the specific model's fit. The work in [10] does local search in the small vicinity of the current solution.…”