Golden Gate: Bridging The Resource-Efficiency Gap Between ASICs and FPGA Prototypes

Abstract

We present Golden Gate, an FPGA-based simulation tool that decouples the timing of an FPGA host platform from that of the target RTL design. In contrast to previous work in static time-multiplexing of FPGA resources, Golden Gate employs the Latency-Insensitive Bounded Dataflow Network (LI-BDN) formalism to decompose the simulator into subcomponents, each of which may be independently and automatically optimized. This structure allows Golden Gate to support a broad class of optimizations that improve resource utilization by implementing FPGA-hostile structures over multiple cycles, while the LI-BDN formalism ensures that the simulator still produces bit-and cycle-exact results. To verify that these optimizations are implemented correctly, we also present lime, a model-checking tool that provides a push-button flow for checking whether optimized subcomponents adhere to an associated correctness specification, while also guaranteeing forward progress. Finally, we use Golden Gate to generate a cycle-exact simulator of a multi-core SoC, where we reduce LUT utilization by up to 26% by coercing multi-ported, combinationally read memories into simulation models backed by time-multiplexed block RAMs, enabling us to simulate 50% more cores on a single FPGA.

UCLID5: Multi-Modal Formal Modeling, Verification, and Synthesis

“…The UCLID5 framework was first proposed in 2018 [40], itself a major evolution of the much older UCLID system [7], one of the first satisfiability modulo theories (SMT) based modeling and verification tools. Since that publication [40], which laid out the vision for the tool and described a preliminary implementation, the utility of the tool has been demonstrated on several problem classes (e.g., [9,30,8]), such as for verifying security across the hardware-software interface. The syntax has been extended and state-of-the-art methods for syntax-guided synthesis (SyGuS) have also been integrated into the tool [33], including new capabilities for satisfiability and synthesis modulo oracles [37].…”

“…This work was supported in part by NSF grant 1837132, the DARPA grant FA8750-20-C-0156 (LOGiCS), by the Qualcomm Innovation Fellowship, and by Amazon and Intel. 9 https://github.com/uclid-org/riscverifier [24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39] constrain the next nondeterministic value of state to one that complies with the language semantics. The operational modeling using the next block simplifies the specification of constraints including non-decreasing time tags (line 25), unique event per tag (line 27), reaction priority (line 29), connection delay (line [31][32][33][34][35][36], and trigger mechanism (line [38][39][40].…”

UCLID5: Multi-modal Formal Modeling, Verification, and Synthesis

“…The UCLID5 framework was first proposed in 2018 [35], itself a major evolution of the much older UCLID system [6], one of the first satisfiability modulo theories (SMT) based modeling and verification tools. Since that publication [35], which laid out the vision for the tool and described a preliminary implementation, the utility of the tool has been demonstrated on several problem classes (e.g., [7,8,25]), such as for verifying security across the hardware-software interface. The syntax has been extended and state-of-the-art methods for syntaxguided synthesis (SyGuS) have also been integrated into the tool [28], including new capabilities for satisfiability and synthesis modulo oracles [32].…”