Go Ahead: A Partial Reconfiguration Framework

Beckhoff, Christian; Koch, Dirk; Tørresen, Jim

doi:10.1109/fccm.2012.17

Cited by 93 publications

(59 citation statements)

References 12 publications

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“…While GoAhead [8] supports bitstream relocation, its approach does not ensure that relocation will be possible. Indeed, instead of making sure that a specific region will be able to host a module generated for another region, this design flow checks if a relocation is possible and regenerates another partial bitstream for the new region if not.…”

Section: A Bitstream Relocation On Xilinx Fpgasmentioning

confidence: 99%

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AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Lalevée

Horrein

Arzel

et al. 2016

2016 Euromicro Conference on Digital System Design (DSD)

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Abstract-Dynamic and partial reconfiguration of Field Programmable Gate Arrays (FPGA) enable to reuse logic resources for several applications which are scheduled in a sequential order or which are loaded on demand. A fraction of the design on the FPGA is then substituted by another logic function while the rest of the system on the chip stays unaffected. If a design provides several partial reconfigurable areas, the configuration bitstream representing the logic function to be configured in this region has to be adapted to the physical requirements of this chip area. This can be achieved by deploying a repository with all possible configuration bitstreams for all possible regions. It is obvious that storage space can quickly become a limiting parameter in reconfigurable designs. For this purpose, bitstream relocation provides a less storage greedy approach. Only one representation as bitstream of an application needs to be stored. During the configuration process, a relocation algorithm manipulates the bitstream in order to suit it to the respective reconfigurable area. However, reconfigurable regions have to fulfill strong constraints for a relocation to be possible, which makes the selection and placement of reconfigurable regions a complex process. Unfortunately this is not automated by tools so far. In this paper, an approach to automate the development of such relocatable bitstreams is presented along with new algorithms related to relocation specific steps. This approach results in functional designs with minimal intervention from the designer.

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Section: A Bitstream Relocation On Xilinx Fpgasmentioning

confidence: 99%

“…Several algorithms have already been proposed for traditional reconfigurable designs, such as in [8], [10], [11], [12], [13], [14], [15]. However, these algorithms usually outputs very compact static part, i.e.…”

Section: B Automated Floorplanningmentioning

confidence: 99%

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Lalevée

Horrein

Arzel

et al. 2016

2016 Euromicro Conference on Digital System Design (DSD)

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“…In this case, the static system has to provide a communication link for sending corresponding data to the module. For this work, we used the Atlys Spartan-6 demonstration system which is distributed with GOAHEAD [7]. This system provides fine-grained two dimensional module placement including a communication architecture tailored to streaming applications.…”

Section: A Level-0: Static Systemmentioning

confidence: 99%

“…The flow shares techniques known from conventional module-based partial reconfiguration and focus is put on the parts that are specific for allowing hierarchical reconfiguration. This work is based on the GOAHEAD tool [7] in which the static system and the partial modules are implemented independently from each other. Consequently, we will describe the implementation of the static system (level-0), the partial modules (level-1), and the partial submodules (level-2) in different paragraphs.…”

Section: Design Flowmentioning

confidence: 99%

Hierarchical reconfiguration of FPGAs

Koch

Beckhoff

2014

2014 24th International Conference on Field Programmable Logic and Applications (FPL)

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Abstract-Partial reconfiguration allows some applications to substantially save FPGA area by time sharing resources among multiple modules. In this paper, we push this approach further by introducing hierarchical reconfiguration where reconfigurable modules can have reconfigurable submodules. This is useful for complex systems where many modules have common parts or where modules can share components. For such systems, we show that the number of bitstreams and the bitstream storage requirements can be scaled down from a multiplicative to an additive behavior with respect to the number of modules and submodules. A case study consisting of different reconfigurable softcore CPUs and hierarchically reconfigurable custom instruction set extensions demonstrates a 18.7× lower bitstream storage requirement and up to 10× faster reconfiguration speed when using hierarchical reconfiguration instead of using conventional single-level module-based reconfiguration.

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“…This is for instance done by loading and unloading modules as needed [2,3] or by performing dynamic circuit specialisation [4]. This makes it possible to use smaller and cheaper FPGAs to do the same amount of computation as larger FPGAs that do not use partial reconfiguration.…”

Section: Introductionmentioning

confidence: 99%

On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure

Heyse

Stroobandt

Kadlcek

et al. 2014

Lecture Notes in Computer Science

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Abstract. It is common for large hardware designs to have a number of registers or memories of which the contents have to be changed very seldom, e.g. only at startup. The conventional way of accessing these memories is using a low-speed memory bus. This bus uses valuable hardware resources, introduces long, global connections and contributes to routing congestion. Hence, it has an impact on the overall design even though it is only rarely used. A Field-Programmable Gate Array (FPGA) already contains a global communication mechanism in the form of its configuration infrastructure. In this paper we evaluate the use of the configuration infrastructure as a replacement for a low-speed memory bus on the Maxeler HPC platform. We find that by removing the conventional low-speed memory bus the maximum clock frequency of some applications can be improved by 8%. Improvements by 25% and more are also attainable, but constraints of the Xilinx reconfiguration infrastructure prevent fully exploiting these benefits at the moment. We present a number of possible changes to the Xilinx reconfiguration infrastructure and tools that would solve this and make these results more widely applicable.

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Go Ahead: A Partial Reconfiguration Framework

Cited by 93 publications

References 12 publications

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

Hierarchical reconfiguration of FPGAs

On the Impact of Replacing a Low-Speed Memory Bus on the Maxeler Platform, Using the FPGA’s Configuration Infrastructure

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