Global design of analog cells using statistical optimization techniques

Abstract

We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables to design complex analog cells from scratch within reasonable CPU time. Three different specification types are covered: strong constraints on the electrical performance of the cells, weak constraints on this performance, and design objectives. A mathematical cost function is proposed and a bunch of heuristics is given to increase accuracy and reduce CPU time to minimize the cost function. A technique is also presented to yield designs with reduced variability in the performance parameters, under random variations of the transistor technological parameters. Several CMOS analog cells with complexity levels up to 48 transistors are designed for illustration. Measurements from fabricated prototypes demonstrate the suitability of the proposed methodology.

Analog circuit optimization system based on hybrid evolutionary algorithms

“…In addition, the simplifications required in the closed form analytical equations cause low accuracy and incompleteness. On the contrary, simulation-based methods do not rely on analytical equations but on SPICE-like simulations to evaluate the circuit performances in the optimization process, which result in superior accuracy, generality, and ease of use [12][13][14][15]. Therefore, our system is simulation-based.…”

A novel heuristic for multi-objective optimization of analog circuit performances

“…as well as to meet design objectives regarding area, power consumption etc. while satisfying a set of constraints [1]. These optimization problems are thus seldom single-objective ones.…”

“…However these methodologies place the algorithm control in the hands of the user and hence, may pose problems. That is why (analog) designers generally make appeal to simulation based statistical approaches [1,5,8,9,11,12], to ''fixed topology'' tools (also known as fixed schematics because they use design equations associated with a predetermined topology to find values satisfying the user's specifications. See for instance [13][14][15][16][17]), or to some other sizing/optimizing techniques such as those proposed in [18][19][20][21][22][23][24][25].…”

Analog circuit design optimization through the particle swarm optimization technique

“…Common approaches are generally either fixed topology ones or/and statistic-based techniques (see for instance [5][6][7][8]). They generally start with finding a ''good'' DC operating point, which is provided by the analog 'expert' designer.…”